公开(公告)号：US07605447B2

公开(公告)日：2009-10-20

申请号：US11162780

申请日：2005-09-22

申请人： Bruce B. Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

发明人： Bruce B. Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

IPC分类号： H01L29/06 ,  H01L29/04 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S438/973

摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

摘要翻译： 本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。 这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。 衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。 更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于 传输栅晶体管。

公开(公告)号：US20070063278A1

公开(公告)日：2007-03-22

申请号：US11162780

申请日：2005-09-22

申请人： Bruce Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

发明人： Bruce Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

IPC分类号： H01L27/12

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S438/973

摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

摘要翻译： 本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。 这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。 衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。 更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于 传输栅晶体管。

公开(公告)号：US07713807B2

公开(公告)日：2010-05-11

申请号：US11958877

申请日：2007-12-18

申请人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

发明人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US07494861B2

公开(公告)日：2009-02-24

申请号：US12013704

申请日：2008-01-14

申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

公开(公告)号：US06905941B2

公开(公告)日：2005-06-14

申请号：US10250069

申请日：2003-06-02

申请人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Meikei Ieong ,  Wesley C. Natzle

发明人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Meikei Ieong ,  Wesley C. Natzle

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L21/76

CPC分类号： H01L21/84 ,  H01L21/76283

摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

摘要翻译： 提供了一种用于防止在隔离的超薄Si沟道器件的有源器件区域下形成多晶硅的方法。 该方法使用化学氧化物去除（COR）处理步骤来防止托管架形成，而不是采用诸如HF的化学蚀刻剂的常规湿法蚀刻工艺。 还提供了绝缘体上硅（SOI）结构。 该结构包括至少位于掩埋绝缘层上的顶部含Si层; 以及位于顶部含Si层和掩埋绝缘层的一部分中的氧化物填充沟槽隔离区。 顶部含Si层下方没有底切区域。

公开(公告)号：US07678638B2

公开(公告)日：2010-03-16

申请号：US12198857

申请日：2008-08-26

申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

公开(公告)号：US07485506B2

公开(公告)日：2009-02-03

申请号：US11866786

申请日：2007-10-03

申请人： Bruce B. Doris ,  Meikei Ieong ,  Edward J. Nowak ,  Min Yang

发明人： Bruce B. Doris ,  Meikei Ieong ,  Edward J. Nowak ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

摘要翻译： 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：US07459752B2

公开(公告)日：2008-12-02

申请号：US11473757

申请日：2006-06-23

申请人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

发明人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772

摘要： Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations are provided. Such a SOI MOSFET may include a SOI substrate having a SOI layer in which a first portion thereof has a thickness of less than 20 nm; a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having the thickness, the gate electrode having an upper surface and a bottom surface that have the same length or the bottom surface has a length that is greater than the upper surface; and source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to the first portion, and the second portion of the SOI layer is thicker than the first portion.

摘要翻译： 超薄体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET），其中SOI厚度随栅极长度变化而变化，从而最小化通常由SOI引起的阈值电压变化 提供了厚度和栅极长度的变化。 这样的SOI MOSFET可以包括具有SOI层的SOI衬底，其中第一部分的厚度小于20nm; 包括栅电介质的栅极和位于具有厚度的SOI层的第一部分顶部的栅电极，栅极具有具有相同长度或底表面的上表面和底表面，其长度大于 上表面 以及位于SOI层的与第一部分相邻的第二部分中的源极和漏极扩散区，并且SOI层的第二部分比第一部分厚。

公开(公告)号：US07453123B2

公开(公告)日：2008-11-18

申请号：US11676030

申请日：2007-02-16

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US07413941B2

公开(公告)日：2008-08-19

申请号：US11433806

申请日：2006-05-13

申请人： Ying Zhang ,  Bruce B. Doris ,  Thomas Safron Kanarsky ,  Meikei Ieong ,  Jakub Tadeusz Kedzierski

发明人： Ying Zhang ,  Bruce B. Doris ,  Thomas Safron Kanarsky ,  Meikei Ieong ,  Jakub Tadeusz Kedzierski

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

摘要翻译： 公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。 该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。 分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。 该组合允许使用FinFET类型器件进行器件宽度控制。 分段场效应器件为给定的布局区域提供高电流驱动。 分段场效应器件允许制造高性能处理器。