公开(公告)号：US07713807B2

公开(公告)日：2010-05-11

申请号：US11958877

申请日：2007-12-18

申请人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

发明人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US07329923B2

公开(公告)日：2008-02-12

申请号：US10250241

申请日：2003-06-17

申请人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

发明人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

IPC分类号： H01L27/01

CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US20080096330A1

公开(公告)日：2008-04-24

申请号：US11958877

申请日：2007-12-18

申请人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

发明人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L21/84

CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

公开(公告)号：US20050236687A1

公开(公告)日：2005-10-27

申请号：US10830347

申请日：2004-04-22

申请人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

发明人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US07138683B2

公开(公告)日：2006-11-21

申请号：US10967398

申请日：2004-10-18

申请人： Kathryn W. Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

发明人： Kathryn W. Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

IPC分类号： H01L27/01

CPC分类号： H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

摘要： The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。

公开(公告)号：US06830962B1

公开(公告)日：2004-12-14

申请号：US10634446

申请日：2003-08-05

申请人： Kathryn W. Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

发明人： Kathryn W. Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

IPC分类号： H01L2100

CPC分类号： H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

摘要： The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。

公开(公告)号：US07187059B2

公开(公告)日：2007-03-06

申请号：US10875727

申请日：2004-06-24

申请人： Kevin K. Chan ,  Kathryn W. Guarini ,  Meikel Ieong ,  Kern Rim ,  Min Yang

发明人： Kevin K. Chan ,  Kathryn W. Guarini ,  Meikel Ieong ,  Kern Rim ,  Min Yang

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

摘要： A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described including the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HCL acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a root mean square (RMS) surface roughness of less than 0.1 run.

摘要翻译： 描述了用于导电载体的结构和形成方法，其结合了具有在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此形成PS形态层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃来形成拟态或外延层的步骤，并引入含Si气体 和含Ge的气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCL酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质的基体表面，均方根（RMS）的表面粗糙度小于0.1nm。

公开(公告)号：US07485506B2

公开(公告)日：2009-02-03

申请号：US11866786

申请日：2007-10-03

申请人： Bruce B. Doris ,  Meikei Ieong ,  Edward J. Nowak ,  Min Yang

发明人： Bruce B. Doris ,  Meikei Ieong ,  Edward J. Nowak ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

摘要翻译： 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：US07459752B2

公开(公告)日：2008-12-02

申请号：US11473757

申请日：2006-06-23

申请人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

发明人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772

摘要： Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations are provided. Such a SOI MOSFET may include a SOI substrate having a SOI layer in which a first portion thereof has a thickness of less than 20 nm; a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having the thickness, the gate electrode having an upper surface and a bottom surface that have the same length or the bottom surface has a length that is greater than the upper surface; and source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to the first portion, and the second portion of the SOI layer is thicker than the first portion.

摘要翻译： 超薄体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET），其中SOI厚度随栅极长度变化而变化，从而最小化通常由SOI引起的阈值电压变化 提供了厚度和栅极长度的变化。 这样的SOI MOSFET可以包括具有SOI层的SOI衬底，其中第一部分的厚度小于20nm; 包括栅电介质的栅极和位于具有厚度的SOI层的第一部分顶部的栅电极，栅极具有具有相同长度或底表面的上表面和底表面，其长度大于 上表面 以及位于SOI层的与第一部分相邻的第二部分中的源极和漏极扩散区，并且SOI层的第二部分比第一部分厚。

公开(公告)号：US07091069B2

公开(公告)日：2006-08-15

申请号：US10710273

申请日：2004-06-30

申请人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

发明人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

IPC分类号： H01L27/01 ,  H01L21/00 ,  H01L21/356

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772

摘要： A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.

摘要翻译： 提供了一种制造超薄体全耗尽SOI SOI的方法，其中SOI厚度随着栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。 本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。 可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。 如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。 如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。