公开(公告)号：US06803270B2

公开(公告)日：2004-10-12

申请号：US10248819

申请日：2003-02-21

申请人： Omer H. Dokumachi ,  Dureseti Chidambarrao ,  Suryanarayan G. Hegde

发明人： Omer H. Dokumachi ,  Dureseti Chidambarrao ,  Suryanarayan G. Hegde

IPC分类号： H01L218222

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814

摘要： The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

摘要翻译： CMOS电路的速度通过在NFET上施加纵向拉伸应力和PFET上的纵向压缩应力，通过将来自周期表第八列的NFET离子的源和漏极注入氢并将其植入源中来改进 和来自周期表第四和第六列的PFET离子的漏极。

公开(公告)号：US06348388B1

公开(公告)日：2002-02-19

申请号：US09668638

申请日：2000-09-20

申请人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

发明人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  Y10S438/931

摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

摘要翻译： 一种用于制造垂直晶体管的栅极氧化物的工艺。 在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。 沟槽侧壁包括<100>晶面和<110>晶面。 接下来，在沟槽侧壁上形成均匀厚度的牺牲层。 在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入沟槽侧壁的<110>晶面，而不是注入沟槽侧壁的<100>晶面。 然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

公开(公告)号：US6150670A

公开(公告)日：2000-11-21

申请号：US450546

申请日：1999-11-30

申请人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

发明人： Johnathan E. Faltermeier ,  Ulrike Gruening ,  Suryanarayan G. Hegde ,  Rajarao Jammy ,  Brian S. Lee ,  Helmut H. Tews

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/12 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L21/28211 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/28238 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/26506 ,  H01L27/10864 ,  H01L29/4236 ,  H01L29/7813 ,  Y10S438/931

摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

公开(公告)号：US07453123B2

公开(公告)日：2008-11-18

申请号：US11676030

申请日：2007-02-16

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/01

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 在器件层上方的前栅极热氧化物：位于前栅极热氧化物上方并与背栅电极垂直对准的前栅极电极层; 以及设置在所述背栅极热氧化物层上方的与所述第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

公开(公告)号：US07205185B2

公开(公告)日：2007-04-17

申请号：US10663471

申请日：2003-09-15

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

公开(公告)号：US06569781B1

公开(公告)日：2003-05-27

申请号：US10054078

申请日：2002-01-22

申请人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

发明人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

IPC分类号： H01L21265

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/518

摘要： A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

摘要翻译： 在硅衬底上形成氧化物层的方法包括在硅衬底上形成牺牲氧化物层，将氮注入到硅衬底中，退火具有注入氮的硅衬底，从硅衬底去除牺牲氧化层， 硅衬底上的氧化物层。 植入硅中的氮的剂量优选高于1e14cm31 2.退火过程优选在约550℃至约1000℃的温度下进行约1秒至约2秒的时间 小时。

公开(公告)号：US06514843B2

公开(公告)日：2003-02-04

申请号：US09844977

申请日：2001-04-27

申请人： Omer Dokumaci ,  Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Richard Kaplan ,  Mukesh Khare

发明人： Omer Dokumaci ,  Oleg Gluschenkov ,  Suryanarayan G. Hegde ,  Richard Kaplan ,  Mukesh Khare

IPC分类号： H01L214763

CPC分类号： H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28247 ,  H01L29/42368 ,  H01L29/4941

摘要： A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.

公开(公告)号：US06297086B1

公开(公告)日：2001-10-02

申请号：US09266337

申请日：1999-03-11

申请人： Suryanarayan G. Hegde ,  Kam Leung Lee ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Suryanarayan G. Hegde ,  Kam Leung Lee ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.

摘要翻译： 采用准分子激光退火来提高栅极激活和源极/漏极激活的灵活性，并且限制制造沟槽存储半导体存储器件中的高介电常数存储电容器的分解程度。

公开(公告)号：US5875171A

公开(公告)日：1999-02-23

申请号：US704836

申请日：1996-08-28

申请人： David W. Albrecht ,  James William Berberich ,  Suryanarayan G. Hegde ,  Thomas Franklin Roth

发明人： David W. Albrecht ,  James William Berberich ,  Suryanarayan G. Hegde ,  Thomas Franklin Roth

IPC分类号： G11B5/82 ,  G11B5/84 ,  G11B7/24 ,  G11B17/02 ,  G11B33/14 ,  G11B7/26

CPC分类号： G11B17/02 ,  G11B5/82 ,  G11B5/8404 ,  G11B5/8408 ,  G11B7/24003 ,  G11B33/14 ,  G11B7/24

摘要： An interlocking disk apparatus for preventing disk slip in a disk stack of a magnetic or optical disk drive is provided. A textured region within the inner diameter of the disks in the disk stack is forced in tight contact with a conformable adjacent surface, such as a spacer ring, clamp plate, and/or hub flange. The textures on the disks penetrate into and/or through the conformal coatings on the adjacent surfaces, resulting in mechanical interlock that inhibits in-plane displacements of the disks from shock and generally improving interfacial contact of the surfaces within the disk stack, thus requiring lower clamping pressures to the disk stack and resulting in greater disk flatness and minimizing disk distortion. Electrostatic Discharge within the disk stack is prevented by diffusing conductive materials into the polymer conformal coating to increase its electrical conductivity.

摘要翻译： 提供一种用于防止磁盘或磁盘驱动器的盘堆中的盘滑动的互锁盘装置。 磁盘堆叠中的盘的内径内的纹理区域被迫与适形的相邻表面（例如间隔环，夹紧板和/或轮毂凸缘）紧密接触。 磁盘上的纹理穿透相邻表面上的和/或通过相邻表面上的共形涂层，导致机械互锁，其阻止磁盘的平面内位移受到冲击，并且通常改善磁盘堆叠内的表面的界面接触，因此需要较低的 夹紧到磁盘堆叠的压力，并导致更大的磁盘平整度和最小化磁盘失真。 通过将导电材料扩散到聚合物保形涂层中以增加其导电性来防止盘堆内的静电放电。

公开(公告)号：US20080246090A1

公开(公告)日：2008-10-09

申请号：US12119765

申请日：2008-05-13

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

摘要翻译： 提供了具有横向排列的前（上）和后门的双栅极晶体管。 双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。 背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。 晶体管还包括在所述晶体管体的相对侧上的源极和漏极。