公开(公告)号：US09438418B1

公开(公告)日：2016-09-06

申请号：US13102673

申请日：2011-05-06

申请人： Bruce B. Pedersen ,  Ninh D. Ngo

发明人： Bruce B. Pedersen ,  Ninh D. Ngo

IPC分类号： H04L9/08 ,  H04L29/06 ,  H04L9/14

CPC分类号： H04L9/0861 ,  G09C1/00 ,  H04L9/14 ,  H04L9/3239 ,  H04L63/0478 ,  H04L63/06

摘要： Systems and methods relating to generating a key that is difficult to clone are described. The methods include receiving a programmable logic device (PLD) with a first key and applying a one-way hash function to a second key or the first key and the second key to create a third key. The application of the one-way hash function is performed using one or more components hardwired into the PLD. The methods further include storing the third key in the PLD only after using the one or more components to apply the one-way hash function.

摘要翻译： 描述与生成难以克隆的密钥有关的系统和方法。 所述方法包括用第一密钥接收可编程逻辑器件（PLD），并将单向散列函数应用于第二密钥或第一密钥和第二密钥以创建第三密钥。 单向散列函数的应用使用硬连线到PLD中的一个或多个组件来执行。 所述方法还包括仅在使用所述一个或多个组件来应用所述单向散列函数之后将所述第三密钥存储在所述PLD中。

公开(公告)号：US5963049A

公开(公告)日：1999-10-05

申请号：US807561

申请日：1997-02-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

公开(公告)号：US06366121B2

公开(公告)日：2002-04-02

申请号：US09865227

申请日：2001-05-25

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： G06F738

CPC分类号： H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/1776

摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate “lonely register” function in modules of the regions.

摘要翻译： 可编程逻辑阵列集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域以交叉行和列的区域的二维阵列布置在器件上。 几个区域的输出信号共享一组驱动器，用于将区域输出信号应用于在区域之间传送信号的互连导体。 这节省了驱动程序资源，并增加了信号路由的灵活性。 可以使用各种方法来配置互连导体，以便节省互连导体资源。 逻辑区域可以用于直接驱动特定的输入/输出单元，由此简化到I / O单元的信号路由，并且还可能简化I / O单元的结构（例如，通过允许执行某些I / O单元功能 在相关的逻辑区域）。 区域输出信号路由灵活性也可以被增强以促进组合逻辑的同时执行和区域模块中的单独的“孤独寄存器”功能。

公开(公告)号：US5909126A

公开(公告)日：1999-06-01

申请号：US672676

申请日：1996-06-28

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Christopher F. Lane ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Ninh D. Ngo ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/04 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  H03K19/04

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

公开(公告)号：US20070283193A1

公开(公告)日：2007-12-06

申请号：US11737089

申请日：2007-04-18

申请人： David Lewis ,  Ninh D. Ngo ,  Andy L. Lee ,  Joseph Huang

发明人： David Lewis ,  Ninh D. Ngo ,  Andy L. Lee ,  Joseph Huang

IPC分类号： G06F11/10

CPC分类号： G11C29/52 ,  G06F11/1064 ,  H03K19/17764

摘要： Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.

摘要翻译： 检测在存储的配置数据中发生的软错误是否可以被忽略的假阳性的电路，方法和装置，使得不必要地重新加载配置数据或其他补救措施。 一个例子提供了包括错误检测电路和灵敏度处理器的集成电路。 误差检测电路检测出错误。 灵敏度处理器确定是否可以忽略检测到的错误，或者是否开始补救措施，例如提供错误标志，重新配置设备或纠正错误。 灵敏度处理器可以基于是否在配置未使用的电路的存储器单元中发生错误来进行该确定。 灵敏度处理器可以使用错误日志来跟踪可能被忽略的已知错误，使得每次检查配置数据时不需要完成该确定。

公开(公告)号：US08661321B1

公开(公告)日：2014-02-25

申请号：US13618097

申请日：2012-09-14

申请人： Ninh D. Ngo

发明人： Ninh D. Ngo

IPC分类号： G11C29/00

CPC分类号： H03M13/1525 ,  G06F11/1004 ,  G11C7/1006 ,  G11C2029/0411

摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

摘要翻译： 提供错误检测和错误位置确定电路，用于检测和定位可编程集成电路上的随机存取存储器阵列中的软错误。 随机存取存储器阵列包含随机访问存储器单元的行和列。 一些单元载入配置数据，并产生用于编程可编程逻辑的相关区域的静态输出信号。 对阵列的每列计算循环冗余校验错误校正位。 循环冗余校验错误校正位存储在阵列中相应的单元格列中。 在系统中的集成电路的正常操作期间，单元受到由背景辐射引起的软错误。 错误检测和错误位置确定电路使用并行处理来连续监视数据以识别每个错误的行和列位置。

公开(公告)号：US08281215B1

公开(公告)日：2012-10-02

申请号：US12917441

申请日：2010-11-01

申请人： Ninh D. Ngo

发明人： Ninh D. Ngo

IPC分类号： H03M13/00

CPC分类号： H03M13/1525 ,  G06F11/1004 ,  G11C7/1006 ,  G11C2029/0411

摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

摘要翻译： 提供错误检测和错误位置确定电路，用于检测和定位可编程集成电路上的随机存取存储器阵列中的软错误。 随机存取存储器阵列包含随机访问存储器单元的行和列。 一些单元载入配置数据，并产生用于编程可编程逻辑的相关区域的静态输出信号。 对阵列的每列计算循环冗余校验错误校正位。 循环冗余校验错误校正位存储在阵列中相应的单元格列中。 在系统中的集成电路的正常操作期间，单元受到由背景辐射引起的软错误。 错误检测和错误位置确定电路使用并行处理来连续监视数据以识别每个错误的行和列位置。

公开(公告)号：US07844886B1

公开(公告)日：2010-11-30

申请号：US11436967

申请日：2006-05-16

申请人： Ninh D. Ngo

发明人： Ninh D. Ngo

IPC分类号： H03M13/00

CPC分类号： H03M13/1525 ,  G06F11/1004 ,  G11C7/1006 ,  G11C2029/0411

摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

摘要翻译： 提供错误检测和错误位置确定电路，用于检测和定位可编程集成电路上的随机存取存储器阵列中的软错误。 随机存取存储器阵列包含随机访问存储器单元的行和列。 一些单元载入配置数据，并产生用于编程可编程逻辑的相关区域的静态输出信号。 对阵列的每列计算循环冗余校验错误校正位。 循环冗余校验错误校正位存储在阵列中相应的单元格列中。 在系统中的集成电路的正常操作期间，单元受到由背景辐射引起的软错误。 错误检测和错误位置确定电路使用并行处理来连续监视数据以识别每个错误的行和列位置。

公开(公告)号：US08032817B2

公开(公告)日：2011-10-04

申请号：US12608835

申请日：2009-10-29

申请人： Ninh D. Ngo

发明人： Ninh D. Ngo

IPC分类号： H03M13/00

CPC分类号： H03M13/091 ,  G01R31/31816 ,  G01R31/318533 ,  G11C2029/0401 ,  G11C2029/0411 ,  H03K19/17764

摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

摘要翻译： 提供错误检测和错误位置确定电路，用于检测和定位可编程集成电路上的随机存取存储器阵列中的软错误。 随机存取存储器阵列包含随机访问存储器单元的行和列。 一些单元载入配置数据，并产生用于编程可编程逻辑的相关区域的静态输出信号。 对每个阵列的每列计算循环冗余校验错误校正位。 纠错校验位存储在阵列中相应的单元格列中。 在系统中的集成电路的正常操作期间，单元受到由背景辐射引起的软错误。 误差检测和误差位置确定电路包含处理阵列数据列的线性反馈移位寄存器电路。 电路连续处理数据以识别每个错误的行和列位置。

公开(公告)号：US07907460B2

公开(公告)日：2011-03-15

申请号：US12503637

申请日：2009-07-15

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G11C29/00

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。