公开(公告)号：US20160189681A1

公开(公告)日：2016-06-30

申请号：US14582972

申请日：2014-12-24

申请人： Bryan R. White ,  Balaji Vembu ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale

发明人： Bryan R. White ,  Balaji Vembu ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale

IPC分类号： G09G5/18 ,  G06T1/60 ,  G06T1/20

CPC分类号： G09G5/18 ,  G06T1/20 ,  G09G5/026 ,  G09G5/14 ,  G09G5/363 ,  G09G2320/106 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/18 ,  G09G2370/16

摘要： Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.

摘要翻译： 这里描述的是与在“处理器到处理器”切换或事务中的命令和图形上下文从相干到非相干存储器/结构发送相关的确保图形命令和图形上下文被卸载并被调度用于消费的技术。

公开(公告)号：US20190303334A1

公开(公告)日：2019-10-03

申请号：US16447025

申请日：2019-06-20

申请人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

发明人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06T1/20

摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

公开(公告)号：US08166207B2

公开(公告)日：2012-04-24

申请号：US12286187

申请日：2008-09-29

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中复合来自外围设备的第一写请求的方法，用于响应于第一写请求获得处理器复合的信息，以及将第二写请求从处理器复合体发送到 外围设备包括信息。 描述和要求保护其他实施例。

公开(公告)号：US08819305B2

公开(公告)日：2014-08-26

申请号：US12618867

申请日：2009-11-16

申请人： Daren J. Schmidt ,  Bryan R. White

发明人： Daren J. Schmidt ,  Bryan R. White

IPC分类号： G06F13/38 ,  H04L12/56 ,  G06F12/08 ,  G06F13/40 ,  G06F13/42

CPC分类号： H04L47/39 ,  G06F12/0831 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4221 ,  G06F2213/3808 ,  H04L47/30

摘要： In one embodiment, the present invention provides for a layered communication protocol for a serial link, in which a link layer is to receive and forward a message to a protocol layer coupled to the link layer with a minimal amount of buffering and without maintenance of a single resource buffer for adaptive credit pools where all message classes are able to consume credits. By performing a message decode, the link layer is able to steer non-data messages and data messages to separate structures within the protocol layer. Credit accounting for each message type can be handled independently where the link layer is able to return credits immediately for non-data messages. In turn, the protocol layer includes a shared buffer to store all data messages received from the link layer and return credits to the link layer for these messages when the data is removed from the shared buffer. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明提供了用于串行链路的分层通信协议，其中链路层将以最小量的缓冲接收和转发消息到与链路层耦合的协议层，并且不维护 用于自适应信用库的单个资源缓冲区，其中所有消息类都能够消耗信用。 通过执行消息解码，链路层能够引导非数据消息和数据消息来分离协议层内的结构。 每个消息类型的信用记帐可以独立处理，链路层可以立即为非数据消息返回信用。 反过来，协议层包括共享缓冲器，用于存储从链路层接收到的所有数据消息，并且当数据从共享缓冲器中移除时，向这些消息的链路层返回信用。 描述和要求保护其他实施例。

公开(公告)号：US08386668B2

公开(公告)日：2013-02-26

申请号：US13428071

申请日：2012-03-23

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中复合来自外围设备的第一写请求的方法，用于响应于第一写请求获得处理器复合的信息，以及将第二写请求从处理器复合体发送到 外围设备包括信息。 描述和要求保护其他实施例。

公开(公告)号：US20120179842A1

公开(公告)日：2012-07-12

申请号：US13428071

申请日：2012-03-23

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中复合来自外围设备的第一写请求的方法，用于响应于第一写请求获得处理器复合的信息，以及将第二写请求从处理器复合体发送到 外围设备包括信息。 描述和要求保护其他实施例。

公开(公告)号：US07861024B2

公开(公告)日：2010-12-28

申请号：US12286324

申请日：2008-09-30

申请人： Bryan R. White ,  Douglas Moran

发明人： Bryan R. White ,  Douglas Moran

IPC分类号： G06F13/00

CPC分类号： G06F1/3203

摘要： In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，一种方法包括从外围设备接收处理器复合体中的传入的已发布的事务，确定事务是否是中断事务，并且如果是，则将其路由到第一队列，否则将其路由到第二队列。 描述和要求保护其他实施例。

公开(公告)号：US08396996B2

公开(公告)日：2013-03-12

申请号：US13428079

申请日：2012-03-23

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

公开(公告)号：US20100082852A1

公开(公告)日：2010-04-01

申请号：US12286187

申请日：2008-09-29

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中复合来自外围设备的第一写请求的方法，用于响应于第一写请求获得处理器复合的信息，以及将第二写请求从处理器复合体发送到 外围设备包括信息。 描述和要求保护其他实施例。

公开(公告)号：US07145568B2

公开(公告)日：2006-12-05

申请号：US11028595

申请日：2005-01-05

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G09G5/36 ,  G06F15/167 ,  G06F12/00

CPC分类号： G09G5/363 ,  G06F3/14 ,  G06F12/1027 ,  G09G2360/12 ,  G09G2360/125

摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller coupled to the memory controller hub to store graphics data.

摘要翻译： 存储器控制器集线器包括适于对数据执行图形操作的图形子系统和适于存储图形子系统可用于存储图形数据的物理存储器中的位置的高速缓存，并且可用于耦合到存储器控制器集线器的图形控制器以存储图形 数据。