公开(公告)号：US06857066B2

公开(公告)日：2005-02-15

申请号：US09990899

申请日：2001-11-16

申请人： Bryant E. Bigbee ,  Shivnandan Kaushik ,  Frank Binns

发明人： Bryant E. Bigbee ,  Shivnandan Kaushik ,  Frank Binns

IPC分类号： G06F1/04 ,  G06F9/30

CPC分类号： G06F9/30003

摘要： A method and apparatus comprising setting a register to a value executing a processing instruction to interpret the value and the at least one register verifying that the interpretation of the processing instruction is valid to ensure the at least one register contains a valid at least one string scanning the string in the register for multiplier scanning the string in the register for a frequency and determining a maximum operating frequency with the multiplier and frequency.

摘要翻译： 一种方法和装置，包括将寄存器设置为执行处理指令的值以解释所述值，并且所述至少一个寄存器验证所述处理指令的解释是否有效以确保所述至少一个寄存器包含有效的至少一个字符串扫描 寄存器中的字符串用于乘法器扫描寄存器中的字符串频率，并用乘数和频率确定最大工作频率。

公开(公告)号：US06920581B2

公开(公告)日：2005-07-19

申请号：US10038323

申请日：2002-01-02

申请人： Bryant E. Bigbee ,  Shivnandan Kaushik ,  James B. Crossland

发明人： Bryant E. Bigbee ,  Shivnandan Kaushik ,  James B. Crossland

IPC分类号： G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/00

CPC分类号： G06F11/1641 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/0793 ,  G06F11/2028

摘要： A method and apparatus for functional redundancy check mode recovery is disclosed. A method in accordance with one embodiment includes detecting an event associated with a device within a data processing system, initiating a platform-independent device removal sequence for the device in response to detecting the event, virtually ejecting the device from the data processing system in response to initiating the platform-independent device removal sequence, and servicing the event associated with the device in response to virtually ejecting the device from the data processing system.

摘要翻译： 公开了一种用于功能冗余校验模式恢复的方法和装置。 根据一个实施例的方法包括检测与数据处理系统内的设备相关联的事件，响应于检测到事件而启动用于设备的与平台无关的设备移除序列，从而响应于数据处理系统虚拟地弹出设备 启动与平台无关的设备移除序列，以及响应于从数据处理系统虚拟地弹出设备来服务与设备相关联的事件。

公开(公告)号：US06349380B1

公开(公告)日：2002-02-19

申请号：US09267796

申请日：1999-03-12

申请人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

发明人： Shahrokh Shahidzadeh ,  Bryant E. Bigbee ,  David B. Papworth ,  Frank Binns ,  Robert P. Colwell

IPC分类号： G06F9355

CPC分类号： G06F9/342 ,  G06F12/0292

摘要： A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

摘要翻译： 用于提供超过32位的扩展线性地址的微处理器。 可以通过将线性地址与段选择器扩展连接，或者通过连接来自两个寄存器的值来提供扩展线性地址。 执行线性地址到物理地址的分级转换，其中层级中的层数取决于线性地址是否是扩展线性地址。

公开(公告)号：US20170177429A1

公开(公告)日：2017-06-22

申请号：US14977354

申请日：2015-12-21

申请人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US08607235B2

公开(公告)日：2013-12-10

申请号：US11027445

申请日：2004-12-30

申请人： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

发明人： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC分类号： G06F9/46

CPC分类号： G06F9/4843

摘要： Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

摘要翻译： 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。

公开(公告)号：US20130073835A1

公开(公告)日：2013-03-21

申请号：US13675910

申请日：2012-11-13

申请人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F9/30

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20080133898A1

公开(公告)日：2008-06-05

申请号：US11230721

申请日：2005-09-19

申请人： Chris J. Newburn ,  Dion Rodgers ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Gautham N. Chinya ,  Xiang Zou ,  Hong Wang

发明人： Chris J. Newburn ,  Dion Rodgers ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Gautham N. Chinya ,  Xiang Zou ,  Hong Wang

IPC分类号： G06F9/30

CPC分类号： G06F9/461

摘要： A technique for managing context state information. At least one embodiment includes a plurality of save area segments to store a plurality of machine context state information. One embodiment includes at least one in-use bit vector to indicate status of the plurality of machine context information.

摘要翻译： 一种用于管理上下文状态信息的技术。 至少一个实施例包括多个保存区段以存储多个机器上下文状态信息。 一个实施例包括至少一个用于指示多个机器上下文信息的状态的使用中位向量。

公开(公告)号：US08566567B2

公开(公告)日：2013-10-22

申请号：US13529630

申请日：2012-06-21

申请人： Chris J. Newburn ,  Robert Knight ,  Robert Geva ,  Dion Rodgers ,  Xiang Zou ,  Hong Wang ,  Bryant E. Bigbee ,  Ittai Anati

发明人： Chris J. Newburn ,  Robert Knight ,  Robert Geva ,  Dion Rodgers ,  Xiang Zou ,  Hong Wang ,  Bryant E. Bigbee ,  Ittai Anati

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/542 ,  G06F11/348 ,  G06F11/3612 ,  G06F2201/86 ,  G06F2201/885

摘要： Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

公开(公告)号：US20130219154A1

公开(公告)日：2013-08-22

申请号：US13837923

申请日：2013-03-15

申请人： Don A. Van Dyke ,  Michael Mishaeli ,  Ittai Anati ,  Baiju V. Patel ,  Will Deutsch ,  Rajesh Shah ,  Gilbert Neiger ,  James B. Crossland ,  Chris J. Newburn ,  Bryant E. Bigbee ,  Muhammad Faisal Azeem ,  John L. Reid ,  Dion Rodgers

发明人： Don A. Van Dyke ,  Michael Mishaeli ,  Ittai Anati ,  Baiju V. Patel ,  Will Deutsch ,  Rajesh Shah ,  Gilbert Neiger ,  James B. Crossland ,  Chris J. Newburn ,  Bryant E. Bigbee ,  Muhammad Faisal Azeem ,  John L. Reid ,  Dion Rodgers

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30003 ,  G06F9/30101 ,  G06F9/461

摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

公开(公告)号：US08010969B2

公开(公告)日：2011-08-30

申请号：US11151809

申请日：2005-06-13

申请人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

发明人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

IPC分类号： G06F3/00 ,  G06F9/46 ,  G06F7/38

CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

摘要翻译： 监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。 本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少 减少与用户级线程相关联的性能抑制事件。