公开(公告)号：US20110014756A1

公开(公告)日：2011-01-20

申请号：US12889826

申请日：2010-09-24

申请人： Byoung-Keon PARK ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

发明人： Byoung-Keon PARK ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/78615 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/3244

摘要： A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

摘要翻译： 薄膜晶体管包括：基板; 设置在所述基板上的半导体层，并且包括沟道区，源极和漏极区以及在所述源极和漏极区的边缘处形成的具有第一杂质的边缘区，以及可选地在所述沟道区中; 绝缘半导体层的栅极绝缘层; 通过所述栅极绝缘层与所述半导体层绝缘的栅电极; 以及电连接到半导体层的源极和漏极。

公开(公告)号：US20080217620A1

公开(公告)日：2008-09-11

申请号：US12045172

申请日：2008-03-10

申请人： Byoung-Keon PARK ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

发明人： Byoung-Keon PARK ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L29/78615 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/3244

摘要： A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

摘要翻译： 薄膜晶体管包括：基板; 设置在所述基板上的半导体层，并且包括沟道区，源极和漏极区以及在所述源极和漏极区的边缘处形成的具有第一杂质的边缘区，以及可选地在所述沟道区中; 绝缘半导体层的栅极绝缘层; 通过所述栅极绝缘层与所述半导体层绝缘的栅电极; 以及电连接到半导体层的源极和漏极。

公开(公告)号：US08569764B2

公开(公告)日：2013-10-29

申请号：US12045172

申请日：2008-03-10

申请人： Byoung-Keon Park ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

发明人： Byoung-Keon Park ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/78615 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/3244

摘要： A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

公开(公告)号：US08530290B2

公开(公告)日：2013-09-10

申请号：US12889826

申请日：2010-09-24

申请人： Byoung-Keon Park ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

发明人： Byoung-Keon Park ,  Tae-hoon Yang ,  Jin-Wook Seo ,  Sei-Hwan Jung ,  Ki-Yong Lee

IPC分类号： H01L21/00

CPC分类号： H01L29/78615 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/3244

摘要： A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

摘要翻译： 薄膜晶体管包括：基板; 设置在所述基板上的半导体层，并且包括沟道区，源极和漏极区以及在所述源极和漏极区的边缘处形成的具有第一杂质的边缘区，以及可选地在所述沟道区中; 绝缘半导体层的栅极绝缘层; 通过所述栅极绝缘层与所述半导体层绝缘的栅电极; 以及电连接到半导体层的源极和漏极。

公开(公告)号：US08409887B2

公开(公告)日：2013-04-02

申请号：US12713846

申请日：2010-02-26

申请人： Byoung-Keon Park ,  Tae-Hoon Yang ,  Jin-Wook Seo ,  Soo-Beom Jo ,  Dong-Hyun Lee ,  Kil-Won Lee ,  Maxim Lisachenko ,  Yun-Mo Chung ,  Bo-Kyung Choi ,  Jong-Ryuk Park ,  Ki-Yong Lee

发明人： Byoung-Keon Park ,  Tae-Hoon Yang ,  Jin-Wook Seo ,  Soo-Beom Jo ,  Dong-Hyun Lee ,  Kil-Won Lee ,  Maxim Lisachenko ,  Yun-Mo Chung ,  Bo-Kyung Choi ,  Jong-Ryuk Park ,  Ki-Yong Lee

IPC分类号： H01L21/00

CPC分类号： H01L51/52 ,  H01L27/3265 ,  H01L2227/323

摘要： An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.

公开(公告)号：US20120000986A1

公开(公告)日：2012-01-05

申请号：US13009279

申请日：2011-01-19

申请人： Min-Jae JEONG ,  Ki-Yong Lee ,  Jong-Won Hong ,  Heung-Yeol Na ,  Eu-Gene Kang ,  Seok-Rak Chang ,  Jin-Wook Seo ,  Tae-Hoon Yang ,  Yun-Mo Chung ,  Byung-Soo Soo ,  Byoung-Keon Park ,  Dong-Hyun Lee ,  Kil-Won Lee ,  Won-Bong Baek ,  Jong-Ryuk Park ,  Bo-Kyung Choi ,  Ivan Maidanchuk ,  Jae-Wan Jung

发明人： Min-Jae JEONG ,  Ki-Yong Lee ,  Jong-Won Hong ,  Heung-Yeol Na ,  Eu-Gene Kang ,  Seok-Rak Chang ,  Jin-Wook Seo ,  Tae-Hoon Yang ,  Yun-Mo Chung ,  Byung-Soo Soo ,  Byoung-Keon Park ,  Dong-Hyun Lee ,  Kil-Won Lee ,  Won-Bong Baek ,  Jong-Ryuk Park ,  Bo-Kyung Choi ,  Ivan Maidanchuk ,  Jae-Wan Jung

IPC分类号： F24D5/00

CPC分类号： C23C16/4481 ,  C23C16/45525 ,  C23C16/52

摘要： A canister for a deposition apparatus and a deposition apparatus using the same, and more particularly, a canister for a deposition apparatus that can provide a uniform amount of source material contained in a reaction gas supplied into a deposition chamber and improve safety in the supply of the source material, and a deposition apparatus using the canister. The deposition apparatus includes a deposition chamber; a canister supplying a reaction gas into the deposition chamber; and a carrier gas supplier for supplying a carrier gas into the canister, in which the canister includes a main body, a heating unit heating the main body and a temperature measuring unit disposed under the main body.

摘要翻译： 一种用于沉积设备的罐和使用其的沉积设备，更具体地，涉及一种用于沉积设备的罐，其可以提供均匀量的源材料，所述源材料包含在供应到沉积室中的反应气体中，并且提高了供应 源材料和使用该罐的沉积装置。 沉积设备包括沉积室; 向所述沉积室供应反应气体的罐; 以及载体气体供给器，用于将载气供应到罐中，其中罐包括主体，加热单元加热主体，温度测量单元设置在主体下方。

公开(公告)号：US07935586B2

公开(公告)日：2011-05-03

申请号：US12853263

申请日：2010-08-09

申请人： Tae-Hoon Yang ,  Ki-Yong Lee ,  Jin-Wook Seo ,  Byoung-Keon Park

发明人： Tae-Hoon Yang ,  Ki-Yong Lee ,  Jin-Wook Seo ,  Byoung-Keon Park

IPC分类号： H01L21/84

CPC分类号： H01L29/78654 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78675 ,  H01L29/78696

摘要： A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern which is formed on the substrate, the semiconductor layer pattern having a channel layer of which no seed exists and no gram boundary exists; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film. A method for fabricating the thin film transistor includes forming an amorphous silicon layer on a substrate; forming a semiconductor layer pattern having a channel layer in which no seed exists and no grain boundary exists by crystallizing and patterning the amorphous silicon layer; forming a gate insulating film on the semiconductor layer pattern; and forming a gate electrode on the gate insulating film.

摘要翻译： 通过均匀控制结晶催化剂的低浓度和控制结晶位置，使得不存在晶种并且不存在晶界，或者在薄膜晶体管的沟道层中存在一个晶界，开发出具有改善的特性和均匀性的薄膜晶体管。 薄膜晶体管包括基板; 形成在所述基板上的半导体层图案，所述半导体层图案具有不存在种子的沟道层，并且不存在晶界; 形成在半导体层图案上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。 一种薄膜晶体管的制造方法，包括在基板上形成非晶硅层; 形成具有不存在种子的沟道层的半导体层图案，并且通过对非晶硅层进行结晶和图案化而不存在晶界; 在半导体层图案上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极。

公开(公告)号：US20110020990A1

公开(公告)日：2011-01-27

申请号：US12853263

申请日：2010-08-09

申请人： Tae-Hoon Yang ,  Ki-Yong Lee ,  Jin-Wook Seo ,  Byoung-Keon Park

发明人： Tae-Hoon Yang ,  Ki-Yong Lee ,  Jin-Wook Seo ,  Byoung-Keon Park

IPC分类号： H01L21/336

CPC分类号： H01L29/78654 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78675 ,  H01L29/78696

摘要： A thin film transistor that has improved characteristics and uniformity is developed by uniformly controlling low concentration of crystallization catalyst and controlling crystallization position so that no seed exists and no grain boundary exists, or one grain boundary exists in a channel layer of the thin film transistor. The thin film transistor includes a substrate; a semiconductor layer pattern which is formed on the substrate, the semiconductor layer pattern having a channel layer of which no seed exists and no gram boundary exists; a gate insulating film formed on the semiconductor layer pattern; and a gate electrode formed on the gate insulating film. A method for fabricating the thin film transistor includes forming an amorphous silicon layer on a substrate; forming a semiconductor layer pattern having a channel layer in which no seed exists and no grain boundary exists by crystallizing and patterning the amorphous silicon layer; forming a gate insulating film on the semiconductor layer pattern; and forming a gate electrode on the gate insulating film.

摘要翻译： 通过均匀控制结晶催化剂的低浓度和控制结晶位置，使得不存在晶种并且不存在晶界，或者在薄膜晶体管的沟道层中存在一个晶界，开发出具有改善的特性和均匀性的薄膜晶体管。 薄膜晶体管包括基板; 形成在所述基板上的半导体层图案，所述半导体层图案具有不存在种子的沟道层，并且不存在晶界; 形成在半导体层图案上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。 一种薄膜晶体管的制造方法，包括在基板上形成非晶硅层; 形成具有不存在种子的沟道层的半导体层图案，并且通过对非晶硅层进行结晶和图案化而不存在晶界; 在半导体层图案上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极。

公开(公告)号：US07815734B2

公开(公告)日：2010-10-19

申请号：US11457491

申请日：2006-07-14

申请人： Byoung-Keon Park ,  Jin-Wook Seo ,  Tae-Hoon Yang ,  Ki-Yong Lee

发明人： Byoung-Keon Park ,  Jin-Wook Seo ,  Tae-Hoon Yang ,  Ki-Yong Lee

IPC分类号： H01L21/04 ,  C30B25/12

CPC分类号： H01L29/66757 ,  H01L27/1277 ,  H01L27/1281 ,  H01L29/04 ,  H01L29/78675

摘要： Provided are a thin film transistor and method of fabricating the same, in which an amorphous silicon layer is formed on a substrate, a capping layer containing a metal catalyst having a different concentration according to its thickness is formed on the amorphous silicon layer, the capping layer is patterned to form a capping layer pattern, and the amorphous silicon layer is crystallized, such that the density and position of seeds formed at an interface between the amorphous silicon layer and the capping layer pattern is controlled, thereby improving the size and uniformity of grains, and in which polycrystalline silicon of desired size and uniformity is selectively formed at a desired position by one crystallization process, resulting in a thin film transistor having excellent and desired properties.

摘要翻译： 本发明提供一种薄膜晶体管及其制造方法，其中在基板上形成非晶硅层，在非晶硅层上形成包含不同浓度的金属催化剂的覆盖层 图案化以形成覆盖层图案，并且使非晶硅层结晶化，使得在非晶硅层和覆盖层图案之间的界面处形成的晶种的密度和位置受到控制，从而提高了非晶硅层的尺寸和均匀性 晶粒，并且其中通过一次结晶工艺在期望的位置选择性地形成所需尺寸和均匀性的多晶硅，导致具有优异和期望性能的薄膜晶体管。

公开(公告)号：US07795082B2

公开(公告)日：2010-09-14

申请号：US11741273

申请日：2007-04-27

申请人： Tae-Hoon Yang ,  Ki-Yong Lee ,  Jin-Wook Seo ,  Byoung-Keon Park

发明人： Tae-Hoon Yang ,  Ki-Yong Lee ,  Jin-Wook Seo ,  Byoung-Keon Park

IPC分类号： H01L21/00

CPC分类号： H01L21/02672 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/3226 ,  H01L27/1277 ,  H01L27/1288

摘要： A method of fabricating a CMOS thin film transistor includes: providing a substrate; forming an amorphous silicon layer on the substrate; performing a first annealing process on the substrate and crystallizing the amorphous silicon layer into a polysilicon layer; patterning the polysilicon layer to form first and second semiconductor layers; implanting first impurities into the first and second semiconductor layers; implanting second impurities into the first or second semiconductor layer; and performing a second annealing process on the semiconductor layers to remove the metal catalyst remaining in the first or second semiconductor layer, on which the second impurities are implanted, wherein the first impurities are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the second impurities are implanted at a dose of 1×1011/cm2 to 3×1015/cm2.

摘要翻译： 制造CMOS薄膜晶体管的方法包括：提供衬底; 在所述基板上形成非晶硅层; 在所述衬底上进行第一退火处理并将所述非晶硅层结晶成多晶硅层; 图案化多晶硅层以形成第一和第二半导体层; 将第一杂质注入到第一和第二半导体层中; 将第二杂质注入第一或第二半导体层; 以及对所述半导体层进行第二退火处理，以去除留在其中注入所述第二杂质的所述第一或第二半导体层中的金属催化剂，其中所述第一杂质以6×10 13 / cm 2至5× 1015 / cm2，第1杂质以1×10 11 / cm 2的剂量注入3×1015 / cm 2。