公开(公告)号：US5913045A

公开(公告)日：1999-06-15

申请号：US576452

申请日：1995-12-20

申请人： Byron Gillespie ,  Scott Tetrick ,  Bruce Young

发明人： Byron Gillespie ,  Scott Tetrick ,  Bruce Young

IPC分类号： G06F13/24 ,  G06F13/00 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An element of a multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge (P2P). The invention is part of a design that consolidates a high performance processor (the local processor) and other processing elements into a single system which utilizes a local memory. Four PCI interrupt inputs are provided which can be routed to either local processor interrupt inputs or to PCI Interrupt output pins. In this manner, a server designer is able to connect the PCI interrupts directly to the local processor without any jumpers to provide configuration. Additionally, by providing software which would execute on the local processor, the local processor system can intercept the PCI interrupts and process the low level interrupts to create an intelligent I/O subsystem. A simple multiplexor is used to direct the PCI interrupts inputs to the local processor or directs the PCI interrupt inputs directly to the PCI interrupt outputs. The PCI interrupt inputs would be interrupts from PCI devices connected to the secondary PCI bus or PCI add-in cards connected to the secondary PCI bus. The PCI outputs would go directly to an interrupt controller which supports the host processor interrupt structure. This PCI interrupt output mechanism supports the ability to have the local processor intercept the PCI interrupts, determine if the local processor should process the interrupt or forward the interrupt upstream to the host.

摘要翻译： 将高性能处理器集成到PCI到PCI总线桥（P2P）中的多功能设备的元件。 本发明是将高性能处理器（本地处理器）和其他处理元件合并为利用本地存储器的单个系统的设计的一部分。 提供了四个PCI中断输入，可以将其连接到本地处理器中断输入或PCI中断输出引脚。 以这种方式，服务器设计人员能够将PCI中断直接连接到本地处理器，而无需任何跳线来提供配置。 另外，通过提供将在本地处理器上执行的软件，本地处理器系统可以拦截PCI中断并处理低级中断以创建智能I / O子系统。 一个简单的多路复用器用于将PCI中断输入引导到本地处理器，或将PCI中断输入直接引导到PCI中断输出。 PCI中断输入将是连接到辅助PCI总线的PCI设备或连接到辅助PCI总线的PCI附加卡的中断。 PCI输出将直接连接到支持主机处理器中断结构的中断控制器。 这种PCI中断输出机制支持本地处理器拦截PCI中断的能力，确定本地处理器是否应该处理中断或将中断转发到主机。

公开(公告)号：US5751975A

公开(公告)日：1998-05-12

申请号：US580130

申请日：1995-12-28

申请人： Byron Gillespie ,  Marc Goldschmidt ,  Terry Sych ,  Bruce Young

发明人： Byron Gillespie ,  Marc Goldschmidt ,  Terry Sych ,  Bruce Young

IPC分类号： G06F13/10 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/105 ,  G06F13/404

摘要： A method and apparatus for interfacing a device which is compliant to a first bus protocol to a second bus having a second protocol and for providing virtual functions through an intelligent bridge. The interface apparatus is coupled to the first bus and the second bus. The interface device detects a configuration cycle on the second bus and translates the configuration cycle into a corresponding cycle in a format understandable by the first bus. The bus cycle is executed on the first bus. A local processor is interrupted by the interface apparatus. A verification and correction program is executed by the local processor to restore configuration header values if the executed bus cycle violated the protocol of the second bus. The interface apparatus insures that requests for access to the first bus are blocked during the execution of the verification and correction program.

摘要翻译： 一种用于将符合第一总线协议的设备连接到具有第二协议的第二总线并用于通过智能桥提供虚拟功能的方法和装置。 接口装置耦合到第一总线和第二总线。 接口设备检测第二总线上的配置周期，并将配置周期以第一总线可理解的格式转换为相应的周期。 总线周期在第一个总线上执行。 本地处理器被接口设备中断。 如果执行的总线周期违反了第二总线的协议，则本地处理器执行验证和校正程序来恢复配置头值。 接口装置确保在执行验证和校正程序期间阻止访问第一总线的请求。

公开(公告)号：US5835784A

公开(公告)日：1998-11-10

申请号：US611802

申请日：1996-03-06

申请人： Byron Gillespie ,  Bruce Young

发明人： Byron Gillespie ,  Bruce Young

IPC分类号： G06F13/36 ,  G06F1/10 ,  G06F9/445 ,  G06F13/40 ,  G06F13/42 ,  G06F15/177

CPC分类号： G06F13/4045 ,  G06F1/10

摘要： A method and system for booting a first processor from a remote memory. In response to a reset signal, a processor which has no associated local memory is prevented from executing code and particularly its boot sequence. Because the first processor is prevented from initializing its environment, configuration cycles from a host processor should be prevented from configuring that environment until the first processor has booted. By preventing the host processor from configuring, the first processor environment's integrity is protected. Because the first processor has no local memory, address cycles generated to access local memory would normally go unclaimed on a local bus. An interface between the local bus and the remote memory is configured to claim the local memory address range from the local bus. Once the first processor is enabled, the local memory addresses are used to access the remote memory to return the necessary boot code.

摘要翻译： 一种用于从远程存储器引导第一处理器的方法和系统。 响应于复位信号，防止没有关联的本地存储器的处理器执行代码，特别是其启动顺序。 由于第一个处理器无法初始化其环境，因此应防止从主机处理器的配置周期配置该环境，直到第一个处理器启动为止。 通过防止主机处理器的配置，第一处理器环境的完整性受到保护。 因为第一个处理器没有本地存储器，所以产生访问本地存储器的地址周期通常在本地总线上无人认领。 本地总线和远程存储器之间的接口被配置为从本地总线声明本地存储器地址范围。 启用第一个处理器后，本地内存地址将用于访问远程内存以返回必要的启动代码。

公开(公告)号：US5898858A

公开(公告)日：1999-04-27

申请号：US535626

申请日：1995-09-28

申请人： Byron Gillespie

发明人： Byron Gillespie

IPC分类号： G06F11/26 ,  G06F11/36 ,  G06F9/455

CPC分类号： G06F11/261 ,  G06F11/3652

摘要： A method and apparatus for providing overlay memory support for ball grid array (BGA) microprocessor packages. A emulator having an overlay memory and an emulator probe is provided. The emulator is connected via the emulator probe to a target printed circuit board (e.g., adapter card). This target board includes a local processor, a local memory, a memory controller, and a local processor bus that couples them together. The local processor, local processor bus, and memory controller are integrated into a BGA chip package. Typically, the local processor executes software programs stored in the local memory. Upon receipt of a first signal, the memory controller disables the local memory and allows the emulator to drive data from the overlay memory onto the local processor bus so that the local processor may execute software programs included in the overlay memory.

摘要翻译： 一种用于为球栅阵列（BGA）微处理器封装提供覆盖存储器支持的方法和装置。 提供了具有覆盖存储器和仿真器探针的仿真器。 仿真器通过仿真器探针连接到目标印刷电路板（例如，适配器卡）。 该目标板包括本地处理器，本地存储器，存储器控制器和将它们耦合在一起的本地处理器总线。 本地处理器，本地处理器总线和存储器控制器集成到BGA芯片封装中。 通常，本地处理器执行存储在本地存储器中的软件程序。 在接收到第一信号时，存储器控制器禁用本地存储器并允许仿真器将数据从覆盖存储器驱动到本地处理器总线上，使得本地处理器可以执行包括在覆盖存储器中的软件程序。

公开(公告)号：US5859987A

公开(公告)日：1999-01-12

申请号：US536156

申请日：1995-09-29

申请人： Byron Gillespie ,  Barry Davis

发明人： Byron Gillespie ,  Barry Davis

IPC分类号： G06F13/40

CPC分类号： G06F13/4027

摘要： An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.

摘要翻译： 一种用于在包括集成处理器的多功能智能桥中提供多种配置模式的集成电路。 提供耦合到第一外部总线的第一电路，用于响应于重试信号选择性地产生到第一外部总线上的重试周期。 提供了耦合到本地处理器的第二电路，用于响应于复位信号选择性地复位集成在智能桥中的本地处理器。 第一和第二电路结合重试信号和复位信号，选择性地为多功能智能桥提供多种配置复位模式之一。

公开(公告)号：US5713044A

公开(公告)日：1998-01-27

申请号：US575663

申请日：1995-12-19

申请人： Byron Gillespie ,  Elliot Garbus ,  William Futral

发明人： Byron Gillespie ,  Elliot Garbus ,  William Futral

IPC分类号： G06F13/28 ,  G06F15/02

CPC分类号： G06F13/28

摘要： Dynamic appending of chain descriptors is described with reference to a computer system having a host processor, a DMA unit, a host memory and an external memory wherein the DMA unit controls transference of data between the host memory and the external memory based upon data transference parameters specified in chain descriptors created by the host processor and stored as data structures within the host memory. In accordance with one method and apparatus described herein, dynamic appending of chain descriptors is achieved by employing a resume bit stored within a register of the DMA unit. The host processor, upon creating a new group of chain descriptors to be appended to a previous group, updates a link value within a last chain descriptor of the previous group to point to the first chain descriptor of the new group and also sets the resume bit within the DMA unit. The DMA unit reads chain descriptor parameters, including link values, they perform a data transfer operation specified by the chain descriptor parameters. Upon completion of the transfer operation, the DMA unit examines the resume bit and, if set, the DMA unit rereads the link value for the current chain descriptor. If the resume bit has not been reset, the DMA unit merely proceeds to process the next chain descriptor specified by the previously read link value or, if that link value is a null value, the DMA unit merely terminates operation. In an alternative embodiment described herein, the host processor updates link values but does not set a resume bit within the DMA unit. Rather, the DMA unit initially reads all parameters for a chain descriptor except for the link value. Then, after completion of the data transfer operation specified by the chain descriptor, the data unit reaccesses the chain descriptor to read the link value. Hence, if the link value is updated by the host processor while the DMA unit is processing a chain descriptor, the DMA unit will nevertheless access the updated link value upon completion of the data transference operation. Method and apparatus embodiments are described herein.

公开(公告)号：US5630102A

公开(公告)日：1997-05-13

申请号：US359057

申请日：1994-12-19

申请人： Thomas M. Johnson ,  Aravindh Bakthavathsalu ,  Richard Brunner ,  Eliot Garbus ,  Byron Gillespie ,  Stephen J. Strazdus

发明人： Thomas M. Johnson ,  Aravindh Bakthavathsalu ,  Richard Brunner ,  Eliot Garbus ,  Byron Gillespie ,  Stephen J. Strazdus

IPC分类号： G06F11/36 ,  G06F9/455

CPC分类号： G06F11/3656

摘要： A microprocessor system utilizing an in-circuit emulator (ICE) to aid in testing and debugging by an external emulator. The microprocessor operates in two modes. One mode is emulation mode in which the microprocessor outputs trace information for allowing the emulator to reconstruct microprocessor execution, and the other mode is interrogation mode where the microprocessor ceases emulation mode, and allows the emulator to modify the state of the microprocessor or interrogate it. An ICEBRK signal is provided on the microprocessor to better handle transition from emulation to interrogation mode. An address mark counter and generator is provided to force the microprocessor to automatically issue an address mark message which includes the location of the microprocessor's instruction pointer. An AMCTRL bit may be further provided to allow a human user to selectively inhibit the issuance of an address mark. An ICELOCK signal is provided on the microprocessor to control the writing of control registers during hardware and software initialization that the microprocessor performs. A MSGFRM signal is provided to aid the emulator in capturing trace information generated at high frequencies (in excess of 40 MHz).

摘要翻译： 利用在线仿真器（ICE）的微处理器系统可以帮助外部仿真器进行测试和调试。 微处理器工作在两种模式。 一种模式是仿真模式，其中微处理器输出用于允许仿真器重构微处理器执行的跟踪信息，另一种模式是询问模式，其中微处理器停止仿真模式，并允许仿真器修改微处理器的状态或询问它。 在微处理器上提供了一个+ E，ovs ICEBRK + EE信号，以更好地处理从仿真到询问模式的转换。 提供地址标记计数器和发生器以迫使微处理器自动发出包括微处理器指令指针位置的地址标记消息。 可以进一步提供AMCTRL位以允许人类用户选择性地禁止发出地址标记。 在微处理器上提供了一个+ E，ovs ICELOCK + EE信号，以控制微处理器执行的硬件和软件初始化期间控制寄存器的写入。 提供A + E，ovs MSGFRM + EE信号以帮助仿真器捕获在高频（超过40 MHz）下生成的跟踪信息。