公开(公告)号：US07675374B2

公开(公告)日：2010-03-09

申请号：US12111555

申请日：2008-04-29

申请人： Byung Hun Min ,  Young Ho Kim ,  Byoung Gun Choi ,  Seok Bong Hyun

发明人： Byung Hun Min ,  Young Ho Kim ,  Byoung Gun Choi ,  Seok Bong Hyun

IPC分类号： H03L5/00

CPC分类号： H03L5/00 ,  H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： Provided is a voltage controlled oscillator to which a switching bias technique is applied so as to lower flicker noise of a bias circuit and enhance phase noise characteristics, thereby reducing the overall chip area to make it possible to achieve integration. A common mode voltage applied to the bias circuit is negatively fed back to an oscillation waveform. Therefore, it is possible to stabilize the magnitude of the oscillation waveform of the voltage controlled oscillator with respect to a change in an external condition.

摘要翻译： 提供了一种施加了开关偏压技术的压控振荡器，以便降低偏置电路的闪烁噪声并增强相位噪声特性，由此减小整个芯片面积以实现集成。 施加到偏置电路的共模电压被反馈回振荡波形。 因此，可以相对于外部条件的变化来稳定压控振荡器的振荡波形的大小。

公开(公告)号：US20080122538A1

公开(公告)日：2008-05-29

申请号：US11999421

申请日：2007-12-04

申请人： Seong Su Park ,  Byoung Gun Choi ,  Byung Hun Min

发明人： Seong Su Park ,  Byoung Gun Choi ,  Byung Hun Min

IPC分类号： H03F3/45 ,  H03H5/00

CPC分类号： H03H11/32 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45766 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/453 ,  H03F2203/45291 ,  H03F2203/45302 ,  H03F2203/45364 ,  H03F2203/45532

摘要： Provided is a wideband active balun circuit based on a differential amplifier. The active balun circuit is configured to compensate for unbalance between two differential signals and can be applied to wideband systems, such as software defined radio (SDR) systems or ultra wideband (UWB) systems. Also, when signal unbalance is caused by changes in process conditions, such as temperature, errors in amplitude and phase between the two differential signals can be finely tuned by adjusting a voltage tuning terminal outside a chip, so that the active balun circuit can simply solve the unbalance between the two differential signals. Furthermore, input transistors that constitute a pair of differential amplifiers are provided in a cascode structure to prevent the occurrence of signal leakage and self-mixture.

摘要翻译： 提供了一种基于差分放大器的宽带有源平衡 - 不平衡转换电路。 主动平衡 - 不平衡变换器电路被配置为补偿两个差分信号之间的不平衡，并且可以应用于诸如软件定义无线电（SDR）系统或超宽带（UWB）系统的宽带系统。 此外，当信号不平衡是由诸如温度等过程条件的变化引起时，通过调整芯片外部的电压调谐端可以精细地调节两个差分信号之间的幅度和相位误差，使得主动平衡 - 不平衡转换电路可以简单地解决 两个差分信号之间的不平衡。 此外，构成一对差分放大器的输入晶体管以共源共栅结构提供，以防止信号泄漏和自混合的发生。

公开(公告)号：US07538618B2

公开(公告)日：2009-05-26

申请号：US11999421

申请日：2007-12-04

申请人： Seong Su Park ,  Byoung Gun Choi ,  Byung Hun Min

发明人： Seong Su Park ,  Byoung Gun Choi ,  Byung Hun Min

IPC分类号： H03F3/45

CPC分类号： H03H11/32 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45766 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/453 ,  H03F2203/45291 ,  H03F2203/45302 ,  H03F2203/45364 ,  H03F2203/45532

摘要： Provided is a wideband active balun circuit based on a differential amplifier. The active balun circuit is configured to compensate for unbalance between two differential signals and can be applied to wideband systems, such as software defined radio (SDR) systems or ultra wideband (UWB) systems. Also, when signal unbalance is caused by changes in process conditions, such as temperature, errors in amplitude and phase between the two differential signals can be finely tuned by adjusting a voltage tuning terminal outside a chip, so that the active balun circuit can simply solve the unbalance between the two differential signals. Furthermore, input transistors that constitute a pair of differential amplifiers are provided in a cascode structure to prevent the occurrence of signal leakage and self-mixture.

摘要翻译： 提供了一种基于差分放大器的宽带有源平衡 - 不平衡转换电路。 主动平衡 - 不平衡变换器电路被配置为补偿两个差分信号之间的不平衡，并且可以应用于诸如软件定义无线电（SDR）系统或超宽带（UWB）系统的宽带系统。 此外，当信号不平衡是由诸如温度等过程条件的变化引起时，通过调整芯片外部的电压调谐端可以精细地调节两个差分信号之间的幅度和相位误差，使得主动平衡 - 不平衡转换电路可以简单地解决 两个差分信号之间的不平衡。 此外，构成一对差分放大器的输入晶体管以共源共栅结构提供，以防止信号泄漏和自混合的发生。

公开(公告)号：US08193842B2

公开(公告)日：2012-06-05

申请号：US13344513

申请日：2012-01-05

申请人： Byung Hun Min ,  Hyun Kyu Yu

发明人： Byung Hun Min ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/085 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183 ,  H03L2207/06 ,  H03L2207/50

摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

公开(公告)号：US20110150138A1

公开(公告)日：2011-06-23

申请号：US12970899

申请日：2010-12-16

申请人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

发明人： Jung Woo PARK ,  Young Jae Lee ,  Hyun Kyu Yu ,  Byung Hun Min ,  Seong Do Kim ,  Hoai Nam Nguyen ,  Sang Gug Lee

IPC分类号： H03K9/00

CPC分类号： H04L25/08 ,  H03D7/1441 ,  H03D7/1458 ,  H03H19/004

摘要： A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

摘要翻译： 直接转换接收机包括：高线性混频器装置，包括：采样单元，根据采样频率对输入电流进行采样;以及缓冲单元，其具有低输入阻抗，从采样器单元接收输出信号，放大接收信号 ，并输出电流信号; 以及滤波器装置对来自混频器装置的输出信号进行抽取，并对抽取的信号进行FIR滤波。

公开(公告)号：US07961038B2

公开(公告)日：2011-06-14

申请号：US12631637

申请日：2009-12-04

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03B1/00

CPC分类号： G05B1/03

摘要： A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

摘要翻译： 提供了数字比例积分环路滤波器。 第一比例放大单元将相位误差值乘以第一比例环路增益，并且第一积分放大单元将相位误差累积值乘以第一积分环路增益。 第二比例放大单元将相位误差值乘以第二比例环路增益，第二积分放大单元将相位误差累积值乘以第二积分环路增益。 第一偏移值生成单元通过从第一比例环增益中减去第二比例环增益并将结果值乘以相位误差平均值来生成第一偏移值，第二偏移值生成单元通过减去第二偏移值生成单位生成第二偏移值 来自第一积分环路增益的第二积分环路增益，并将得到的值乘以相位误差累积平均值。

公开(公告)号：US08115525B2

公开(公告)日：2012-02-14

申请号：US12626554

申请日：2009-11-25

申请人： Byung Hun Min ,  Hyun Kyu Yu

发明人： Byung Hun Min ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/085 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183 ,  H03L2207/06 ,  H03L2207/50

摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

摘要翻译： 提供了一个频率合成器。 频率合成器包括根据控制位调节输出频率的频率振荡器; 具有预设的最小分频比的可编程分频器，所述编程分频器以可分分频比划分所述频率振荡器的输出频率; 接收可编程分频器的输出信号的计数器单元和参考频率，以在参考频率的一个周期期间对可编程分频器的输出信号的上升沿进行计数以产生计数值，并且当计数值 是1，并且当计数值为2时输出第二命中信号; 以及相位检测单元，输出通过从从计数值和参考频率获得的锁定相位的分数误差中减去可编程分频器的输出信号的分数误差而获得的控制位。

公开(公告)号：US07999707B2

公开(公告)日：2011-08-16

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一至第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US20100134335A1

公开(公告)日：2010-06-03

申请号：US12629020

申请日：2009-12-01

申请人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

发明人： Mi Jeong Park ,  Byung Hun Min ,  Ja Yol Lee ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： G04F10/06 ,  H03L7/085 ,  H03L2207/50

摘要： An apparatus for compensating for an error of a time-to-digital converter (TDC) is disclosed to receive a delay phase from a phase detector including the TDC and a phase error including a TDC error and compensate for the TDC error to have a time resolution higher by N times (N is a natural number). The apparatus includes: a fragmenting and multiplying unit fragmenting the delay phase by N times (N is a natural number) to generate first to (N−1)th fragmented delay phases; an adding unit adding each of the first to the (N−1)th fragmented delay phases to the phase error to generate first to (N−1)th phase errors; and a comparison unit acquiring a phase error compensation value nearest to an actual phase error from the phase error and the first to (N−1)th phase errors.

摘要翻译： 公开了用于补偿时间 - 数字转换器（TDC）的误差的装置，以从包括TDC的相位检测器和包括TDC误差的相位误差接收延迟相位并补偿TDC误差以具有时间 分辨率提高N倍（N是自然数）。 该装置包括：分段和乘法单元，将延迟相位分片N次（N是自然数），以产生第一到第（N-1）个分段延迟相位; 加法单元将第一到第（N-1）个分段延迟相位中的每一个相加到相位误差，以产生第一到第（N-1）个相位误差; 以及比较单元从相位误差和第一到第（N-1）个相位误差获取最接近实际相位误差的相位误差补偿值。

公开(公告)号：US08611466B2

公开(公告)日：2013-12-17

申请号：US13309873

申请日：2011-12-02

申请人： Young-Jae Lee ,  Byung Hun Min ,  Nguyen Hoai Nam

发明人： Young-Jae Lee ,  Byung Hun Min ,  Nguyen Hoai Nam

IPC分类号： H04L27/00

CPC分类号： H04L27/3809

摘要： Provided is a discrete time receiver having a structure capable of processing various broadband signals. The discrete time receiver uses a discrete time filter having a sampling frequency in a constant range so as to process a signal having an input frequency in a wide range and a wide bandwidth, so that it is possible to reduce current consumption and the area of the discrete time receiver. Since the discrete time receiver is easily integrated with a digital device, it is easy to design a chip using system on chip (SoC).

摘要翻译： 提供了具有能够处理各种宽带信号的结构的离散时间接收机。 离散时间接收机使用具有恒定范围的采样频率的离散时间滤波器，以处理具有宽范围和宽带宽的输入频率的信号，从而可以减少电流消耗和 离散时间接收机。 由于离散时间接收器易于与数字设备集成，所以使用片上系统（SoC）设计芯片很容易。