公开(公告)号：US06338989B1

公开(公告)日：2002-01-15

申请号：US09630717

申请日：2000-08-02

申请人： Byung-Chul Ahn ,  Soon-Sung Yoo ,  Young-Hoon Ha ,  Yong-Wan Kim

发明人： Byung-Chul Ahn ,  Soon-Sung Yoo ,  Young-Hoon Ha ,  Yong-Wan Kim

IPC分类号： H01L2184

CPC分类号： H01L29/66765 ,  H01L27/12

摘要： A 4-mask method of manufacturing an array substrate. First and second masks form a gate line, a gate pad, a data line and a data pad. The data line has a protrusion near a crossing of the gate and data lines. A third mask forms a transparent electrode layer, a source electrode, a drain electrode, a pixel electrode, and exposes channel area. The transparent electrode layer has a similar shape as the data line and the data pad, but a smaller area than the data line and a greater area than the data pad. A second insulating layer is formed over the structure. A fourth mask patterns the second insulating layer to cover the gate line and the gate pad, the first and second insulating layer are patterned to form a gate pad contact hole, and the first insulating layer between the data line and the pixel electrode is patterned.

摘要翻译： 一种制造阵列基板的4掩模方法。 第一和第二掩模形成栅极线，栅极焊盘，数据线和数据焊盘。 数据线在栅极和数据线的交叉点附近具有突起。 第三掩模形成透明电极层，源电极，漏电极，像素电极，并露出通道区域。 透明电极层具有与数据线和数据焊盘相似的形状，但是与数据线相比较小的面积和比数据焊盘更大的面积。 在该结构上形成第二绝缘层。 第四掩模图案化第二绝缘层以覆盖栅极线和栅极焊盘，第一和第二绝缘层被图案化以形成栅极焊盘接触孔，并且数据线和像素电极之间的第一绝缘层被图案化。

公开(公告)号：US06862051B2

公开(公告)日：2005-03-01

申请号：US10397261

申请日：2003-03-27

申请人： Byung-Chul Ahn ,  Soon-Sung Yoo ,  Yong-Wan Kim

发明人： Byung-Chul Ahn ,  Soon-Sung Yoo ,  Yong-Wan Kim

IPC分类号： G02F1/136 ,  G02F1/1362

CPC分类号： G02F1/13458 ,  G02F1/136213 ,  G02F1/136227

摘要： A liquid crystal display, and a method of manufacturing thereof, includes providing a substrate; depositing sequentially a first metal layer and a first insulating layer on the substrate; patterning the first metal layer and the first insulating layer using a first mask to form a gate line and a first gate insulating layer; depositing sequentially a second gate insulating layer, a pure semiconductor layer, a doped semiconductor layer and a second metal layer over the whole substrate; patterning the second metal layer using a second mask to form a data line, source and drain electrodes, a capacitor electrode, the capacitor electrode overlapping a portion of the gae line; etching the doped semiconductor layer between the source and drain electrodes to form a channel region; depositing a third insulating layer over the whole substrate; patterning the third insulating layer using a third mask to form a passivation film, the passivation film having a smaller width than the data line and covering the source and drain electrodes and exposing a portion of the drain electrode and the capacitor electrode; depositing a transparent conductive material layer over the whole substrate; and patterning the transparent conductive material layer using a fourth mask to pixel electrode, the pixel electrode contacting the drain electrode.

摘要翻译： 液晶显示器及其制造方法包括提供基板; 在基板上依次沉积第一金属层和第一绝缘层; 使用第一掩模对第一金属层和第一绝缘层进行构图以形成栅极线和第一栅极绝缘层; 在整个衬底上依次沉积第二栅绝缘层，纯半导体层，掺杂半导体层和第二金属层; 使用第二掩模图案化第二金属层以形成数据线，源极和漏极，电容器电极，电容器电极与gae线的一部分重叠; 蚀刻源极和漏极之间的掺杂半导体层以形成沟道区; 在整个衬底上沉积第三绝缘层; 使用第三掩模对第三绝缘层进行图案化以形成钝化膜，所述钝化膜具有比所述数据线更小的宽度并且覆盖所述源电极和漏电极并暴露所述漏电极和所述电容器电极的一部分; 在整个基板上沉积透明导电材料层; 以及使用第四掩模到像素电极对所述透明导电材料层进行图案化，所述像素电极与所述漏极接触。

公开(公告)号：US06559920B1

公开(公告)日：2003-05-06

申请号：US09694285

申请日：2000-10-24

申请人： Byung-Chul Ahn ,  Soon-Sung Yoo ,  Yong-Wan Kim

发明人： Byung-Chul Ahn ,  Soon-Sung Yoo ,  Yong-Wan Kim

IPC分类号： G02F11343

CPC分类号： G02F1/13458 ,  G02F1/136213 ,  G02F1/136227

摘要： The present invention discloses a method of manufacturing a liquid crystal display device, including: providing a substrate; depositing sequentially a first metal layer and a first insulating layer on the substrate; patterning the first metal layer and the first insulating layer using a first mask to form a gate line and a first gate insulating layer; depositing sequentially a second gate insulating layer, a pure semiconductor layer, a doped semiconductor layer and a second metal layer over the whole substrate; patterning the second metal layer using a second mask to form a data line, source and drain electrodes, a capacitor electrode, the capacitor electrode overlapping a portion of the gate line; etching the doped semiconductor layer between the source and drain electrodes to form a channel region; depositing a third insulating layer over the whole substrate; patterning the third insulating layer using a third mask to form a passivation film, the passivation film having a smaller width than the data line and covering the source and drain electrodes and exposing a portion of the drain electrode and the capacitor electrode; depositing a transparent conductive material layer over the whole substrate; and patterning the transparent conductive material layer using a fourth mask to pixel electrode, the pixel electrode contacting the drain electrode.

摘要翻译： 本发明公开了一种制造液晶显示装置的方法，包括：提供基板; 在基板上依次沉积第一金属层和第一绝缘层; 使用第一掩模对第一金属层和第一绝缘层进行构图以形成栅极线和第一栅极绝缘层; 在整个衬底上依次沉积第二栅绝缘层，纯半导体层，掺杂半导体层和第二金属层; 使用第二掩模图案化第二金属层以形成数据线，源极和漏极，电容器电极，电容器电极与栅极线的一部分重叠; 蚀刻源极和漏极之间的掺杂半导体层以形成沟道区; 在整个衬底上沉积第三绝缘层; 使用第三掩模对第三绝缘层进行图案化以形成钝化膜，所述钝化膜具有比所述数据线更小的宽度并且覆盖所述源电极和漏电极并暴露所述漏电极和所述电容器电极的一部分; 在整个基板上沉积透明导电材料层; 以及使用第四掩模到像素电极对所述透明导电材料层进行图案化，所述像素电极与所述漏极接触。

公开(公告)号：US06906760B2

公开(公告)日：2005-06-14

申请号：US09917861

申请日：2001-07-31

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC分类号： G02F1/1333 ,  G02F1/1362 ,  G02F1/136

CPC分类号： G02F1/136286 ,  G02F2001/136263

摘要： A liquid crystal display device includes a substrate, a thin film transistor disposed on the substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode, a gate line arranged in a first direction on the substrate, the gate line connected with the gate electrode of the thin film transistor, a gate insulation layer disposed on the substrate and covering the gate line and the gate electrode of the thin film transistor, an intrinsic semiconductor layer disposed on the gate insulation layer, an extrinsic semiconductor layer disposed on the intrinsic semiconductor layer, a data line arranged in a second direction substantially perpendicular to the first direction disposed on the extrinsic semiconductor layer, the data line connected to the source electrode of the thin film transistor, first and second dummy metal layers formed over the gate line and arranged on opposite sides of the data line, a passivation layer covering the data line, the source electrode, the drain electrode and the first and second dummy metal layers, and a pixel electrode located at a pixel region defined by an intersection of the gate line and the data line, the pixel electrode contacting the drain electrode of the thin film transistor.

摘要翻译： 液晶显示装置包括基板，设置在基板上的薄膜晶体管，薄膜晶体管，其包括栅电极，源电极和漏电极，在基板上沿第一方向排列的栅极线，栅极线 与所述薄膜晶体管的栅电极连接，栅极绝缘层，设置在所述基板上并覆盖所述薄膜晶体管的栅极线和栅极，设置在所述栅极绝缘层上的本征半导体层，设置在所述栅极绝缘层上的外部半导体层 在本征半导体层上，沿与第二方向大致垂直的第二方向布置在非本征半导体层上的数据线，与薄膜晶体管的源极连接的数据线，形成在该半导体层上的第一和第二虚设金属层 栅极线并布置在数据线的相对侧，覆盖数据线的钝化层，源极 电极，漏电极和第一和第二虚拟金属层，以及位于由栅极线和数据线的交点限定的像素区域的像素电极，该像素电极与薄膜晶体管的漏电极接触。

公开(公告)号：US06690433B2

公开(公告)日：2004-02-10

申请号：US09923326

申请日：2001-08-08

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hoo-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Dug-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hoo-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Dug-Jin Park ,  Woo-Chae Lee

IPC分类号： G02F11333

CPC分类号： G02F1/136204

摘要： An electrostatic damage preventing apparatus for a thin film transistor array of a liquid crystal display includes a horizontal ground voltage line disposed at a first perimeter portion of the thin film transistor array, a vertical ground voltage line disposed at a second perimeter portion of the thin film transistor array, and a first electrostatic damage-preventing switching device group including parallel connection of at least two electrostatic damage-preventing switching devices to divide and divert an electrostatic voltage applied over the horizontal ground voltage line.

摘要翻译： 一种用于液晶显示器的薄膜晶体管阵列的静电破坏防止装置包括设置在薄膜晶体管阵列的第一周边部分处的水平地电压线，设置在薄膜的第二周边部分的垂直接地电压线 晶体管阵列以及包括至少两个静电损伤防止开关装置的并联连接的第一静电损伤防止开关装置组，以分割和转移施加在水平地电压线上的静电电压。

公开(公告)号：US07027120B2

公开(公告)日：2006-04-11

申请号：US10753449

申请日：2004-01-09

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC分类号： G02F1/1333

CPC分类号： G02F1/133512 ,  G02F1/136286 ,  G02F2001/136295

摘要： A liquid crystal display device and a method of fabricating the same are disclosed in the present invention. More specifically, the method includes the steps forming a gate line on the first substrate sequentially forming a first insulating layer, an amorphous silicon layer, and a metal layer on the first substrate, patterning the metal layer to form a data line, forming a second insulating layer on the data line, patterning the second insulating layer and the amorphous silicon layer to form a passivation layer and an active layer, respectively, forming a pixel electrode at a pixel region defined by the gate and data lines, assembling the first substrate and the second substrate having a black matrix thereon, wherein the black matrix vertically overlaps at least one boundary line defined by different exposures during step-and-repeat exposure processes; and forming a liquid crystal layer between the first and second substrates.

公开(公告)号：US06992364B2

公开(公告)日：2006-01-31

申请号：US10653283

申请日：2003-09-03

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC分类号： H01L29/00

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78669

摘要： A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase a gate line over a said substrate; a data line over the said substrate being perpendicular to the gate line; a passivation layer covering the data line, the passivation layer divided into a residual passivation layer and a etched passivation layer; a doped amorphous silicon layer formed under the data line and corresponding in size to the data line; a pure amorphous silicon layer formed under the doped amorphous silicon layer and having a over-etched portion in the peripheral portions, wherein the over-etched portion is over-etched from the edges of the residual passivation layer toward the inner side; an insulator layer under the pure amorphous silicon layer; a TFT formed near the crossing of the gate line and the data line; and a pixel electrode overlapping the data line and contacting the TFT.

摘要翻译： TFT阵列基板具有PAI图案，并且PAI图案具有纯非晶硅层的过蚀刻部分。 该过蚀刻部分防止像素电极和纯非晶硅层（即有源层）之间的短路。 过蚀刻部分还使孔径比增加了所述衬底上的栅极线; 所述衬底上的数据线垂直于所述栅极线; 覆盖数据线的钝化层，钝化层分为残留钝化层和蚀刻钝化层; 形成在数据线之下且与数据线大小对应的掺杂非晶硅层; 形成在掺杂非晶硅层下面并且在周边部分中具有过蚀刻部分的纯非晶硅层，其中过蚀刻部分从残余钝化层的边缘向内侧被过度蚀刻; 在纯非晶硅层下面的绝缘体层; 形成在栅极线和数据线的交叉点附近的TFT; 以及与数据线重叠并与TFT接触的像素电极。

公开(公告)号：US06798477B2

公开(公告)日：2004-09-28

申请号：US09919614

申请日：2001-08-01

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC分类号： G02F11335

CPC分类号： G02F1/133512 ,  G02F1/136286 ,  G02F2001/136295

摘要： A liquid crystal display device and a method of fabricating the same are disclosed in the present invention. More specifically, the method includes the steps forming a gate line on the first substrate sequentially forming a first insulating layer, an amorphous silicon layer, and a metal layer on the first substrate, patterning the metal layer to form a data line, forming a second insulating layer on the data line, patterning the second insulating layer and the amorphous silicon layer to form a passivation layer and an active layer, respectively, forming a pixel electrode at a pixel region defined by the gate and data lines, assembling the first substrate and the second substrate having a black matrix thereon, wherein the black matrix vertically overlaps at least one boundary line defined by different exposures during step-and-repeat exposure processes; and forming a liquid crystal layer between the first and second substrates.

公开(公告)号：US07428024B2

公开(公告)日：2008-09-23

申请号：US10810659

申请日：2004-03-29

申请人： Soon-Sung Yoo ,  Yong-Wan Kim ,  Yu-Ho Jung ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Yong-Wan Kim ,  Yu-Ho Jung ,  Woo-Chae Lee

IPC分类号： G02F1/1343

CPC分类号： G02F1/1368 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733

摘要： The present invention discloses an array substrate for an active-matrix LCD device and a method of fabricating the same. The array substrate reduces the number of masks typically used in the fabrication process so that reliability is enhanced and the cost is reduced over the conventional device and method. Electric shorts caused by hillocks can be prevented or reduced by incorporating short-preventing sections between the gate line and an overlapping pixel electrode.

摘要翻译： 本发明公开了一种有源矩阵LCD器件用阵列基板及其制造方法。 阵列基板减少了在制造过程中通常使用的掩模的数量，从而提高了可靠性并且降低了成本比传统的装置和方法。 通过在栅极线和重叠像素电极之间并入防短路部分，可以防止或减少由小丘引起的电短路。

公开(公告)号：US06627470B2

公开(公告)日：2003-09-30

申请号：US09779438

申请日：2001-02-09

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hu-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Duk-Jin Park ,  Woo-Chae Lee

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78669

摘要： A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase. a gate line over a said substrate; a data line over the said substrate being perpendicular to the gate line; a passivation layer covering the data line, the passivation layer divided into a residual passivation layer and a etched passivation layer; a doped amorphous silicon layer formed under the data line and corresponding in size to the data line; a pure amorphous silicon layer formed under the doped amorphous silicon layer and having a over-etched portion in the peripheral portions, wherein the over-etched portion is over-etched from the edges of the residual passivation layer toward the inner side; an insulator layer under the pure amorphous silicon layer; a TFT formed near the crossing of the gate line and the data line; and a pixel electrode overlapping the data line and contacting the TFT.

摘要翻译： TFT阵列基板具有PAI图案，并且PAI图案具有纯非晶硅层的过蚀刻部分。 该过蚀刻部分防止像素电极和纯非晶硅层（即有源层）之间的短路。 过蚀刻部分还使孔径比增加。 在所述衬底上的栅极线; 所述衬底上的数据线垂直于所述栅极线; 覆盖数据线的钝化层，钝化层分为残留钝化层和蚀刻钝化层; 形成在数据线之下且与数据线大小对应的掺杂非晶硅层; 形成在掺杂非晶硅层下面并且在周边部分中具有过蚀刻部分的纯非晶硅层，其中过蚀刻部分从残余钝化层的边缘向内侧被过度蚀刻; 在纯非晶硅层下面的绝缘体层; 形成在栅极线和数据线的交叉点附近的TFT; 以及与数据线重叠并与TFT接触的像素电极。