公开(公告)号：US20060028886A1

公开(公告)日：2006-02-09

申请号：US11124341

申请日：2005-05-06

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器减小了较高外围温度的宽度。

公开(公告)号：US07463511B2

公开(公告)日：2008-12-09

申请号：US11723361

申请日：2007-03-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

摘要翻译： 相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。 存储单元阵列包括多个块单元，每个块单元连接在相应的一对字线驱动器之间。 写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。 列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流 的内存块。

公开(公告)号：US20070242503A1

公开(公告)日：2007-10-18

申请号：US11723361

申请日：2007-03-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device comprises a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array comprises a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit comprises a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

摘要翻译： 相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。 存储单元阵列包括多个块单元，每个块单元连接在对应的一对字线驱动器之间。 写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。 列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流 的内存块。

公开(公告)号：US07796425B2

公开(公告)日：2010-09-14

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C11/4193 ,  G11C11/4197

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US20080212362A1

公开(公告)日：2008-09-04

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US07315469B2

公开(公告)日：2008-01-01

申请号：US11124341

申请日：2005-05-06

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C7/22

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器减小了较高外围温度的宽度。

公开(公告)号：US07110286B2

公开(公告)日：2006-09-19

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US20060104102A1

公开(公告)日：2006-05-18

申请号：US11183613

申请日：2005-07-18

申请人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/18

摘要： A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

摘要翻译： 真正的位线可以沿第一方向跨越存储器件的存储器单元区域延伸，并且互补位线可以在与第一方向相反的第二方向跨越存储器单元区域延伸，其中真位线和互补位线 包括位线对。

公开(公告)号：US20050007843A1

公开(公告)日：2005-01-13

申请号：US10889194

申请日：2004-07-12

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/812 ,  G11C29/806

摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

摘要翻译： 一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址 在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

公开(公告)号：US20060274574A1

公开(公告)日：2006-12-07

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.