公开(公告)号：US20060274574A1

公开(公告)日：2006-12-07

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US07110286B2

公开(公告)日：2006-09-19

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

公开(公告)号：US07502251B2

公开(公告)日：2009-03-10

申请号：US11502563

申请日：2006-08-11

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0078 ,  G11C2013/0092

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

摘要翻译： 相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。 相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。 地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程 电路进入结晶状态。 写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变至少一个复位和设置的脉冲电流的脉冲宽度和脉冲计数中的至少一个。

公开(公告)号：US07274586B2

公开(公告)日：2007-09-25

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

公开(公告)号：US20050169093A1

公开(公告)日：2005-08-04

申请号：US10919371

申请日：2004-08-17

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C8/00 ,  G11C16/02

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

摘要翻译： 相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。 相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。 地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程 电路进入结晶状态。 写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变复位和设置脉冲电流中的至少一个的脉冲宽度和脉冲计数中的至少一个。

公开(公告)号：US20050195633A1

公开(公告)日：2005-09-08

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/10 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

公开(公告)号：US20080303016A1

公开(公告)日：2008-12-11

申请号：US12196137

申请日：2008-08-21

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L45/00

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

公开(公告)号：US07427531B2

公开(公告)日：2008-09-23

申请号：US11324112

申请日：2005-12-30

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L21/06

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

公开(公告)号：US07317655B2

公开(公告)日：2008-01-08

申请号：US11327967

申请日：2006-01-09

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

IPC分类号： G11C8/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

摘要翻译： 提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。 半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到 多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

公开(公告)号：US20060164896A1

公开(公告)日：2006-07-27

申请号：US11327967

申请日：2006-01-09

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

IPC分类号： G11C7/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

摘要翻译： 提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。 半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到 多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。