公开(公告)号：US06944089B2

公开(公告)日：2005-09-13

申请号：US10334776

申请日：2002-12-31

申请人： Byung-Hoon Jeong ,  Woo-Seop Jeong ,  Byung-Chul Kim ,  Beob-Rae Cho ,  Seung-Bum Ko

发明人： Byung-Hoon Jeong ,  Woo-Seop Jeong ,  Byung-Chul Kim ,  Beob-Rae Cho ,  Seung-Bum Ko

IPC分类号： G06F1/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  H03K5/13 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.

摘要翻译： 提供一种具有恒定数据输出时间而不管位组织的同步半导体器件，以及调节数据输出时间的方法。 同步半导体器件包括用于接收外部时钟并产生内部时钟的内部时钟发生器，用于响应于位组织信息调整内部时钟的相位并产生数据输出时钟的时钟控制器，以及用于 响应于数据输出时钟将从存储器单元读取的数据输出到外部。 因此，无论盘的摆动如何，都可以防止装载在盘驱动器中的盘的垂直振动。

公开(公告)号：US08045404B2

公开(公告)日：2011-10-25

申请号：US12660439

申请日：2010-02-26

申请人： Byung-Hyun Lee ,  Byung-Sik Moon ,  Seung-Bum Ko

发明人： Byung-Hyun Lee ,  Byung-Sik Moon ,  Seung-Bum Ko

IPC分类号： G11C7/10

CPC分类号： G11C7/18 ,  G11C11/4087 ,  G11C2207/002

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列具有耦合在多个字线和多个位线对之间的多个存储器单元，位线选择电路被配置为在所选择的位线对和本地输入/ 响应于列选择信号的输出线对;本地全局输入/输出门电路，被配置为响应于局部全局输入/输出选择信号在本地输入/输出线对与全局输入/输出线对之间传输数据 以及控制器，被配置为驱动字线，将具有第一电压电平的列选择信号输出到位线选择电路，并输出具有低于第一电压的第二电压电平的局部全局输入/输出选择信号 响应于外部地址信号和外部命令，电平到本地全局输入/输出门电路。

公开(公告)号：US07495973B2

公开(公告)日：2009-02-24

申请号：US11625597

申请日：2007-01-22

申请人： Han-Gyun Jung ,  Seung-Bum Ko

发明人： Han-Gyun Jung ,  Seung-Bum Ko

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C11/4076

摘要： A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.

摘要翻译： 公开了一种用于控制半导体存储器件中的写恢复时间（tWR）的电路和方法。 根据本发明的一个实施例的方法包括接收自动预充电写入命令，以及生成从接收到自动预充电写入命令的时间点延迟到最后数据的时间点的tWR控制信号 片段被写入半导体存储器件中。 因此，由于在写入最后数据的时间点之后，用于控制tWR的电路中的计数器的操作可能被最小化，所以能够降低功耗和时钟噪声。

公开(公告)号：US20100226187A1

公开(公告)日：2010-09-09

申请号：US12660439

申请日：2010-02-26

申请人： Byung-Hyun Lee ,  Byung-Sik Moon ,  Seung-Bum Ko

发明人： Byung-Hyun Lee ,  Byung-Sik Moon ,  Seung-Bum Ko

IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C5/14

CPC分类号： G11C7/18 ,  G11C11/4087 ,  G11C2207/002

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列具有耦合在多个字线和多个位线对之间的多个存储器单元，位线选择电路被配置为在所选择的位线对和本地输入/ 响应于列选择信号的输出线对;本地全局输入/输出门电路，被配置为响应于局部全局输入/输出选择信号在本地输入/输出线对与全局输入/输出线对之间传输数据 以及控制器，被配置为驱动字线，将具有第一电压电平的列选择信号输出到位线选择电路，并输出具有低于第一电压的第二电压电平的局部全局输入/输出选择信号 响应于外部地址信号和外部命令，电平到本地全局输入/输出门电路。