公开(公告)号：US20030151020A1

公开(公告)日：2003-08-14

申请号：US10193589

申请日：2002-07-11

Applicant: Cabot Microelectronics Corporation

Inventor： Jui-Kun Lee ,  Chris C. Yu ,  David G. Mikolas

IPC: A62D001/00 ,  A62C002/00

CPC classification number: B81C1/00611 ,  B81C2201/0123

Abstract: Methods for manufacturing substrates with difficult to polish features using reverse mask etching and chemical mechanical planarization techniques.

Abstract translation: 使用反掩模蚀刻和化学机械平面化技术制造具有难以抛光特征的基板的方法。

公开(公告)号：US20040002207A1

公开(公告)日：2004-01-01

申请号：US10361665

申请日：2003-02-10

Applicant: Cabot Microelectronics Corporation

Inventor： Chris C. Yu

IPC: H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/7682 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76837

Abstract: A method for fabricating a region of low dielectric constant between metal layers of a substrate, such as an integrated circuit, that eliminate or minimize the problems associated with the existing and future low-k materials and processes. The method utilizes a sacrificial layer or an ultra low-k layer to form a major, but not entire, portion of the dielectric layer between the metal layers, using innovative integration schemes and CMP processes.

Abstract translation: 在诸如集成电路的衬底的金属层之间制造低介电常数区域的方法，其消除或最小化与现有和未来的低k材料和工艺相关的问题。 该方法利用创新的集成方案和CMP工艺，利用牺牲层或超低k层在金属层之间形成电介质层的主要部分而不是整个部分。