公开(公告)号：US11580048B1

公开(公告)日：2023-02-14

申请号：US16356939

申请日：2019-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Scott Huss ,  Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Balbeer Singh Rathor

IPC: G06F9/30 ,  G06F13/42 ,  G06F1/12

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

公开(公告)号：US09160582B1

公开(公告)日：2015-10-13

申请号：US14230121

申请日：2014-03-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Scott Huss ,  Chris Moscone ,  James Vandersand, Jr.

IPC: H04B1/10 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H03L7/0807 ,  H03L7/089 ,  H04L7/033 ,  H04L25/03146

Abstract: A system and method are provided for phase recovery of a signal received by a receiver having digital equalization. A sample acquisition unit periodically acquires a plurality of I and Q samples of the received signal. The sample acquisition unit includes a delay portion to enable selective mutual comparisons between a current I sample ID0, a first preceding I samples ID1, and a second preceding I sample ID2. A transition detection unit generates at least one transition detect signal responsive to the ID1, ID0, and Q samples. The transition detect signal indicates a logic state transition in the received signal between the ID1 and ID0 samples. A transition filtering unit generates an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, and selectively passes in response the transition detect signal as a timing output signal.

Abstract translation: 提供了一种用于相位恢复由具有数字均衡的接收机接收的信号的系统和方法。 采样单元周期性地获取接收信号的多个I和Q采样。 样本获取单元包括延迟部分，以使得能够在当前I个样本ID0，前一个I个样本ID1和第二个先前的样本ID2之间进行选择性的相互比较。 转移检测单元响应于ID1，ID0和Q样本产生至少一个转换检测信号。 转移检测信号表示ID1和ID0采样之间的接收信号中的逻辑状态转换。 转换滤波单元产生指示在ID0采样时对接收信号进行过度均衡校正的均衡检测信号，并且响应地选择性地通过转换检测信号作为定时输出信号。