公开(公告)号：US11580048B1

公开(公告)日：2023-02-14

申请号：US16356939

申请日：2019-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Scott Huss ,  Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Balbeer Singh Rathor

IPC: G06F9/30 ,  G06F13/42 ,  G06F1/12

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

公开(公告)号：US09767888B1

公开(公告)日：2017-09-19

申请号：US15396046

申请日：2016-12-30

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Thomas Evan Wilson ,  Balbeer Singh Rathor

IPC: G11C5/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  H03F3/45 ,  H03K17/687

CPC classification number: H03K17/6872 ,  G11C11/4074 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2203/30006 ,  H03F2203/45344

Abstract: Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, four N-type metal oxide semiconductor (NMOS) field effect transistors (FETs), two PMOS FETS, and a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.