公开(公告)号：US5909375A

公开(公告)日：1999-06-01

申请号：US716908

申请日：1996-09-19

申请人： Cameron McClintock ,  James A. Watson ,  Caleb Crome

发明人： Cameron McClintock ,  James A. Watson ,  Caleb Crome

IPC分类号： G01R31/317 ,  G01R31/3181 ,  G06F17/50

CPC分类号： G01R31/3181 ,  G01R31/31713 ,  G06F17/5022 ,  Y02T10/82

摘要： A system and method for making and using integrated circuits using a modeling system. The system utilizes a pin test buffer. The pin test buffer inputs external inputs to a pin, and outputs to the same pin from the device. If contention is noted between the system inputs to the pin, and outputs from the device to the pin, contention error notices are provided to the user.

摘要翻译： 使用建模系统制造和使用集成电路的系统和方法。 系统使用引脚测试缓冲区。 引脚测试缓冲器将引脚的外部输入输入，并从器件输出到同一引脚。 如果在引脚的系统输入和从器件到引脚的输出之间发生争用，则向用户提供争用错误通知。

公开(公告)号：US5384499A

公开(公告)日：1995-01-24

申请号：US123435

申请日：1993-09-17

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。

公开(公告)号：US5241224A

公开(公告)日：1993-08-31

申请号：US691640

申请日：1991-04-25

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

公开(公告)号：US5268598A

公开(公告)日：1993-12-07

申请号：US043146

申请日：1993-03-31

申请人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

发明人： Bruce B. Pedersen ,  David Chiang ,  Francis B. Heile ,  Cameron McClintock ,  Hock-Chuen So ,  James A. Watson

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03R19/177

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。

公开(公告)号：US07800405B2

公开(公告)日：2010-09-21

申请号：US12484665

申请日：2009-06-15

申请人： Andy L. Lee ,  Wanli Chang ,  Cameron McClintock ,  John E. Turner ,  Brian D. Johnson ,  Chiao Kai Hwang ,  Richard Yen-Hsiang Chang ,  Richard G. Cliff

发明人： Andy L. Lee ,  Wanli Chang ,  Cameron McClintock ,  John E. Turner ,  Brian D. Johnson ,  Chiao Kai Hwang ,  Richard Yen-Hsiang Chang ,  Richard G. Cliff

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/063 ,  H03K19/177 ,  H03K19/1778

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

摘要翻译： 提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。 在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。 传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

公开(公告)号：US20070008000A1

公开(公告)日：2007-01-11

申请号：US11498214

申请日：2006-08-01

申请人： Andy Lee ,  Wanli Chang ,  Cameron McClintock ,  John Turner ,  Brian Johnson ,  Chiao Hwang ,  Richard Chang ,  Richard Cliff

发明人： Andy Lee ,  Wanli Chang ,  Cameron McClintock ,  John Turner ,  Brian Johnson ,  Chiao Hwang ,  Richard Chang ,  Richard Cliff

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K17/063 ,  H03K19/177 ,  H03K19/1778

摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

摘要翻译： 提出了用于低电压系统的增强型门控结构，其中V 对由单晶闸管通过的信号范围的影响减小。 在一种布置中，通过施加更高的V门极来提高通过NMOS通孔传播的信号的V门极限极限。 在另一种布置中，V 降低。 传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

公开(公告)号：US06836151B1

公开(公告)日：2004-12-28

申请号：US10781334

申请日：2004-02-17

申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

IPC分类号： H03K190195

CPC分类号： H03K19/018585

摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

摘要翻译： 提供电路以单独配置集成电路的每个I / O以与不同的LVTTL I / O标准兼容。 这可以通过仅一个I / O电源电压完成，其中该电压是特定应用中所需的I / O电压中最高的。 电路通过调节I / O单元的输出电压进行操作，使其高于VOH并低于其符合的LVTTL标准的最大VIH。 由于每个I / O单元都可单独配置，任何I / O都可以驱动到任何LVTTL规范。

公开(公告)号：US06714050B2

公开(公告)日：2004-03-30

申请号：US09898183

申请日：2001-07-03

申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

IPC分类号： H03K190195

CPC分类号： H03K19/17744 ,  H03K19/018585

摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

公开(公告)号：US06278288B1

公开(公告)日：2001-08-21

申请号：US09574371

申请日：2000-05-19

申请人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

发明人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

IPC分类号： G06F738

CPC分类号： H03K19/17752 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1778

摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmable selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.

摘要翻译： 可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。 在设备上提供的用于将多个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。 如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。 可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。

公开(公告)号：US5982195A

公开(公告)日：1999-11-09

申请号：US873169

申请日：1997-06-11

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  Fung Fung Lee ,  Cameron McClintock ,  David W. Mendel ,  Bruce B. Pedersen ,  Srinivas T. Reddy ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19/177 ,  H05K1/00 ,  H05K1/18

CPC分类号： H03K19/17736 ,  H03K19/17792 ,  H05K1/0286 ,  H05K1/181

摘要： A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.

摘要翻译： 可编程逻辑器件具有以这种区域的交叉行和列的二维阵列设置在器件上的可编程逻辑区域。 水平互连导体与每行相关联，并且垂直互连导体与每列相关联。 局部导体分散在每一行的相邻区域对之间，用于向局部导体两侧的区域提供信号。 每个区域的可编程逻辑子区域通常具有本地输出和全局输出。 全局输出仅可用于输出到相对较长距离的水平和垂直导体。 本地输出可额外用作本地反馈和作为到相邻区域的本地连接。