公开(公告)号：US6081139A

公开(公告)日：2000-06-27

申请号：US937907

申请日：1997-09-25

申请人： Carl F. Liepold ,  James T. Doyle

发明人： Carl F. Liepold ,  James T. Doyle

IPC分类号： H01L27/07 ,  H03F3/45 ,  H03K5/24 ,  H03K5/22 ,  H03K17/60

CPC分类号： H03F3/45076 ,  H01L27/0722 ,  H03K5/2481

摘要： The present invention provides a differential amplifier. The differential amplifier includes first and second inputs and an output. The differential amplifier further includes a lateral bipolar transistor. The lateral bipolar transistor includes a well region that has a base region, an emitter region and first and second collector regions. The first and second collector regions are spaced apart from the emitter. The lateral bipolar transistor also includes a first gate, coupled to the first input, to overlay a space between the emitter region and the first collector region. Furthermore, the lateral bipolar transistor includes a second gate, coupled to the second input, to overlay a space between the emitter region and the second collector region. The differential amplifier further includes first and second load devices coupled to the first and second collector regions.

摘要翻译： 本发明提供了一种差分放大器。 差分放大器包括第一和第二输入和输出。 差分放大器还包括横向双极晶体管。 横向双极晶体管包括具有基极区域，发射极区域以及第一和第二集电极区域的阱区域。 第一和第二集电极区域与发射极间隔开。 横向双极晶体管还包括耦合到第一输入的第一栅极，以覆盖发射极区域和第一集电极区域之间的空间。 此外，横向双极晶体管包括耦合到第二输入的第二栅极，以覆盖发射极区域和第二集电极区域之间的空间。 差分放大器还包括耦合到第一和第二集电极区域的第一和第二负载装置。

公开(公告)号：US5841821A

公开(公告)日：1998-11-24

申请号：US764513

申请日：1996-12-12

申请人： James T. Doyle ,  Carl F. Liepold

发明人： James T. Doyle ,  Carl F. Liepold

IPC分类号： H03F3/45 ,  H03H7/01 ,  H03H11/04 ,  H04L5/16 ,  H04L25/03 ,  H04B1/10

CPC分类号： H03H7/1766 ,  H03F3/45085 ,  H03H11/045 ,  H03H7/0115 ,  H04L25/03343 ,  H04L5/16 ,  H03F2203/45371 ,  H03F2203/45574 ,  H03F2203/45612

摘要： The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.

摘要翻译： 本发明提供一种双向低通滤波方法和装置，用于通过传输介质衰减从编码器发送到解码器的数据的基带外分量。 在本发明的一个实施例中，双向低通滤波装置包括具有第一相位响应的切比雪夫滤波器。 该切比雪夫滤波器耦合到具有第二相位响应的相位校正电路。 相位校正电路的第二相位响应被设计为与第一相位响应相反，以便抵消由切比雪夫滤波器引起的数据中组延迟的变化。

公开(公告)号：US5694439A

公开(公告)日：1997-12-02

申请号：US408270

申请日：1995-03-21

申请人： James T. Doyle ,  Carl F. Liepold

发明人： James T. Doyle ,  Carl F. Liepold

IPC分类号： H03F3/45 ,  H03H7/01 ,  H03H11/04 ,  H04L5/16 ,  H04L25/03 ,  H04B1/10

CPC分类号： H03H7/1766 ,  H03F3/45085 ,  H03H11/045 ,  H03H7/0115 ,  H04L25/03343 ,  H04L5/16 ,  H03F2203/45371 ,  H03F2203/45574 ,  H03F2203/45612

摘要： The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.

摘要翻译： 本发明提供一种双向低通滤波方法和装置，用于通过传输介质衰减从编码器发送到解码器的数据的基带外分量。 在本发明的一个实施例中，双向低通滤波装置包括具有第一相位响应的切比雪夫滤波器。 该切比雪夫滤波器耦合到具有第二相位响应的相位校正电路。 相位校正电路的第二相位响应被设计为与第一相位响应相反，以便抵消由切比雪夫滤波器引起的数据中组延迟的变化。

公开(公告)号：US5202590A

公开(公告)日：1993-04-13

申请号：US788491

申请日：1991-11-06

申请人： Carl F. Liepold ,  James T. Doyle

发明人： Carl F. Liepold ,  James T. Doyle

IPC分类号： H03F1/30 ,  H03K5/003 ,  H03K5/08

CPC分类号： H03K5/003 ,  H03F1/301 ,  H03K5/086

摘要： A subthreshold sense circuit for clamping an injected current at the input pins of an integrated circuit device before the injected current causes the voltage at the input pins to exceed the supply voltage by more than a diode's ON voltage. The subthreshold sense circuit is driven to operate in the linear region of the FETs. The subthreshold sense circuit of the present invention comprises level shifters, a subthreshold current source, a reference voltage generator, a subthreshold comparator, and a clamping circuit. The subthreshold current source generates a reference drain current to drive the sense circuit of the present invention in the linear region. A level shifter is connected to an input pin to shift the voltage level of the input pin by a subthreshold voltage level. The reference voltage generator provides a reference voltage to be compared with the subthreshold-shifted input voltage. The subthreshold comparator compares the subthreshold-shifted input voltage with the reference voltage level such that when the subthreshold-shifted input voltage from the input pin exceeds the reference voltage level, the subthreshold comparator will turn on. The clamping circuit is activated by the subthreshold comparator to clamp the input pin to less than one V.sub.D (ON) drop over the supply voltage by sinking the injected current at the input pin when the subthreshold comparator is turned on.

摘要翻译： 在注入电流之前，用于钳位在集成电路器件的输入引脚处的注入电流的亚阈值感测电路使得​​输入引脚处的电压超过电源电压超过二极管的导通电压。 亚阈值检测电路被驱动以在FET的线性区域中工作。 本发明的亚阈值检测电路包括电平移位器，亚阈值电流源，参考电压发生器，亚阈值比较器和钳位电路。 亚阈值电流源产生参考漏极电流，以在线性区域中驱动本发明的感测电路。 电平移位器连接到输入引脚，以将输入引脚的电压电平移位亚阈值电压电平。 参考电压发生器提供与亚阈值移位输入电压进行比较的参考电压。 亚阈值比较器将亚阈值移位输入电压与参考电压电平进行比较，使得当来自输入引脚的亚阈值移位输入电压超过参考电压电平时，子阈值比较器将导通。 钳位电路由次阈值比较器激活，通过在亚阈值比较器导通时将输入引脚上的注入电流吸收，将输入引脚钳位在电源电压下的一个VD（ON）下降。

公开(公告)号：US06198421B1

公开(公告)日：2001-03-06

申请号：US09259650

申请日：1999-02-26

申请人： James T. Doyle ,  Carl F. Liepold

发明人： James T. Doyle ,  Carl F. Liepold

IPC分类号： H03M136

CPC分类号： H03M1/36

摘要： One embodiment of the present invention provides a flash analog-to-digital converter (ADC) based on a feedforward perceptron. The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i=2 . . . N. Each stage i includes an output circuit and 2(i−2) sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign. The output circuit generates an ith digital signal in one of a first and second states when a second sum of the input current and of the second reference current has one of first and second signs respectively.

摘要翻译： 本发明的一个实施例提供一种基于前馈感知器的闪存模数转换器（ADC）。 ADC包括多个N级以提供N个数字信号。 多个N级包括提供与要转换的电压相关的输入电流和参考电流的和的第一级。 如果总和分别具有第一和第二符号之一，则第一级提供第一和第二状态之一的第一数字信号。 多个N级还包括i级，i = 2。 。 。 N.每级i包括一个输出电路和耦合到输出电路的2（i-2）个子级。 每个子级包括耦合在其间的输入和隐藏电路。 输入电路被配置为提供输入电流和第一参考电流的第一和。 当第一和具有第一符号时，每个隐藏电路向输出电路提供第二参考电流。 当输入电流和第二参考电流的第二和分别具有第一和第二符号之一时，输出电路产生第一和第二状态之一的第i个数字信号。

公开(公告)号：US5408235A

公开(公告)日：1995-04-18

申请号：US207040

申请日：1994-03-07

申请人： James T. Doyle ,  Tim Beatty ,  Carl F. Liepold

发明人： James T. Doyle ,  Tim Beatty ,  Carl F. Liepold

IPC分类号： H03H17/02 ,  H03M3/02 ,  H03M1/10

CPC分类号： H03H17/0251 ,  H03M3/462 ,  H03M3/43 ,  H03M3/454

摘要： A "true" 16-bit second order Sigma-Delta based converter that has superior analog components and has a programmable comb filter which is coupled to the digital signal processor. This converter comprises a second order Sigma-Delta modulator and a programmable comb filter. The second order Sigma-Delta modulator dramatically attenuates the baseband quantization noise energy (which in turn increases the resolution of the converter), since its superior amplifiers and comparators enable it to oversample and coarsely quantize the analog input signal at a very high sampling frequency of 12 MHz. The amplifiers are class AB OTAs, which have cross coupled NMOS driven input stages, and cascoded output stages. Also, the common mode voltages are the optimal biasing points, and these voltages are kept constant by a differential input stage, by a PV independent temperature dependent current generator, by optimal device size, and by a common mode feedback circuitry. The programmable comb filter receives the coarsely digitized 1-bit output of the modulator at oversampling frequency F.sub.S, and provides a more accurate representation of the input signal to the DSP at slower sampling rate of F.sub.S /N. In addition, the comb filter uses a 20-bit data path, in order to enable the decimator (which is formed by the comb filter and by the FIR filter) to provide 16 bits of resolution to the DSP. The output of the programmable comb filter is then supplied to an FIR filter which is realized in the DSP, and this filter removes the remaining out-of-baseband noise.

摘要翻译： 一个“真正的”16位二阶Σ-Delta转换器，具有卓越的模拟分量，并具有耦合到数字信号处理器的可编程梳状滤波器。 该转换器包括二阶Σ-Δ调制器和可编程梳状滤波器。 第二级Σ-Δ调制器极大地衰减了基带量化噪声能量（这反过来又增加了转换器的分辨率），因为其优越的放大器和比较器能够以非常高的采样频率对模拟输入信号进行过采样和粗量化 12 MHz。 放大器是AB类ABA，它们具有交叉耦合的NMOS驱动输入级和级联输出级。 此外，共模电压是最佳偏置点，这些电压通过差分输入级，PV独立温度相关电流发生器，最佳器件尺寸以及共模反馈电路保持恒定。 可编程梳状滤波器以过采样频率FS接收调制器的粗略数字化1位输出，并以较慢的FS / N采样速率向DSP提供更精确的输入信号表示。 此外，梳状滤波器使用20位数据路径，以便使能由梳状滤波器和FIR滤波器形成的抽取器能够向DSP提供16位分辨率。 然后将可编程梳状滤波器的输出提供给在DSP中实现的FIR滤波器，该滤波器去除剩余的基带外噪声。

公开(公告)号：US08253405B2

公开(公告)日：2012-08-28

申请号：US12347711

申请日：2008-12-31

申请人： Malay Trivedi ,  Jiang William ,  Brent D. Thomas ,  James T. Doyle ,  Rose Wang

发明人： Malay Trivedi ,  Jiang William ,  Brent D. Thomas ,  James T. Doyle ,  Rose Wang

IPC分类号： G05F1/00

CPC分类号： G06F1/26

摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.

摘要翻译： 通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。 对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。 对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。 平均高侧检测电流和占空比由A-D转换器转换为数字。 数字电路通过调整VR的增益和失调电压来校正感测电流。 调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

公开(公告)号：US20100164477A1

公开(公告)日：2010-07-01

申请号：US12347711

申请日：2008-12-31

申请人： Malay Trivedi ,  Jiang William ,  Brent D. Thomas ,  James T. Doyle ,  Rose Wang

发明人： Malay Trivedi ,  Jiang William ,  Brent D. Thomas ,  James T. Doyle ,  Rose Wang

IPC分类号： G01R19/00 ,  G05F1/10

CPC分类号： G06F1/26

摘要： In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current.

摘要翻译： 通常，一方面，本公开描述了能够感测负载电流的高速多相电压调节器（VR）。 对于每个相支路，VR包括用于在开关元件中镜像电流的电流镜，用于感测电流镜中的高侧电流的电流感测，以及将感测到的高侧电流转换为电压的I-V转换器。 对每个相位支路的高侧检测电流进行平均，并提取VR的占空比。 平均高侧检测电流和占空比由A-D转换器转换为数字。 数字电路通过调整VR的增益和失调电压来校正感测电流。 调整后的感测值除以占空比转换为负载电流，平均负载电流乘以确定总负载电流的相位数。

公开(公告)号：US06771101B1

公开(公告)日：2004-08-03

申请号：US10226523

申请日：2002-08-22

申请人： James T. Doyle

发明人： James T. Doyle

IPC分类号： H03L700

CPC分类号： G05F3/30 ,  Y10S323/901

摘要： A CMOS reference circuit using field effect transistors (FETs) is described. A first plurality of FETs is coupled in series, source node to drain node. A second plurality of FETs is also coupled in series, source node to drain node. The first and second plurality of FETs are coupled such that a specified total voltage drop across the first plurality of FETs is realizable. The combination of the first and second plurality of FETs are usable as a replacement for a resistor. The circuit can also include a FET configured so that it is usable as a replacement for a diode.

摘要翻译： 描述了使用场效应晶体管（FET）的CMOS参考电路。 第一组多个FET串联耦合，源节点到漏极节点。 第二组多个FET串联耦合，源节点到漏极节点。 第一和第二多个FET被耦合，使得跨越第一多个FET的规定的总电压降是可实现的。 第一和第二多个FET的组合可用作电阻器的替代。 该电路还可以包括被配置为使得其可用作二极管的替代物的FET。

公开(公告)号：US06629254B1

公开(公告)日：2003-09-30

申请号：US09607565

申请日：2000-06-29

申请人： Syed R. Naqvi ,  James T. Doyle

发明人： Syed R. Naqvi ,  James T. Doyle

IPC分类号： G06F112

CPC分类号： H03L7/0812 ,  G06F1/10 ,  H03L7/06

摘要： An apparatus includes a memory buffer, a first signal buffer, a locked loop circuit and a feedback circuit. The memory buffer provides a data signal to an output terminal of the memory buffer in response to a first clock signal. The first signal buffer is coupled between the output terminal of the memory buffer and a data line of a bus. The first signal buffer introduces a first delay. The locked loop circuit furnishes the first clock signal to establish a predefined relationship between a phase of a second clock signal and a phase of a third clock signal. The feedback circuit produces the second clock signal in response to the first clock signal. The feedback circuit includes a second signal buffer to introduce a second delay to the second clock, and the second delay is approximately the same as the first delay that is introduced by the first signal buffer.

摘要翻译： 一种装置包括存储器缓冲器，第一信号缓冲器，锁定环路电路和反馈电路。 存储器缓冲器响应于第一时钟信号向存储器缓冲器的输出端提供数据信号。 第一信号缓冲器耦合在存储器缓冲器的输出端和总线的数据线之间。 第一个信号缓冲器引入第一个延迟。 锁定环路电路提供第一时钟信号以建立第二时钟信号的相位和第三时钟信号的相位之间的预定关系。 反馈电路响应于第一时钟信号产生第二时钟信号。 反馈电路包括用于向第二时钟引入第二延迟的第二信号缓冲器，并且第二延迟与由第一信号缓冲器引入的第一延迟大致相同。