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1.发明授权Voltage regulator for programming non-volatile and electrically programmable memory cells 失效用于编程非易失性和电可编程存储单元的电压调节器
公开(公告)号：US5519656A
公开(公告)日：1996-05-21
申请号：US366259
申请日：1994-12-29
申请人： Marco Maccarrone , Marco Olivo , Carla Golla , Silvia Padoan
发明人： Marco Maccarrone , Marco Olivo , Carla Golla , Silvia Padoan
摘要： A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.
摘要翻译： 一种用于编程非易失性存储单元的电压调节器，其包括在第一和第二参考电压之间供电的放大器级，并且具有连接到第一参考电压的电阻分压器的第一输入端和反馈到所述第一参考电压的输出端 通过电流镜输入，源极跟随器晶体管由输出端控制，并通过编程线与单元连接。 还提供了连接到编程线的接地的MOS晶体管和连接在电流镜与第二参考电压之间的相应的电阻路径。
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公开(公告)号：US5748548A
公开(公告)日：1998-05-05
申请号：US711132
申请日：1996-09-09
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.
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3.发明授权Regulation circuit and method for the erasing phase of non-volatile memory cells 失效非易失性存储单元擦除阶段的调节电路和方法
公开(公告)号：US5617356A
公开(公告)日：1997-04-01
申请号：US395361
申请日：1995-02-21
申请人： Carla Golla , Silvia Padoan , Marco Olivo
发明人： Carla Golla , Silvia Padoan , Marco Olivo
摘要： A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
摘要翻译： 一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关， 所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。 还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。 该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。
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公开(公告)号：US5583820A
公开(公告)日：1996-12-10
申请号：US366211
申请日：1994-12-29
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.
摘要翻译： 一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。 比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。 稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。 电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。
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公开(公告)号：US06392469B1
公开(公告)日：2002-05-21
申请号：US08347788
申请日：1994-11-30
申请人： Silvia Padoan , Carla Golla
发明人： Silvia Padoan , Carla Golla
IPC分类号： G05F110
CPC分类号： G05F3/245
摘要： A circuit for generating a stable reference voltage (Vref) as temperature and process parameters vary, including at least one field-effect transistor (M1) and an associated resistive bias element (R) connected in series between a supply voltage (Vcc) and ground (GND), further includes a second field-effect transistor (M2) connected to the first transistor such that the reference voltage (Vref) can be picked up as the difference between the respective threshold voltages of the two transistors. This provides a reference voltage which is uniquely stable against variations in temperature and process parameters.
摘要翻译： 用于产生作为温度和过程参数的稳定参考电压（Vref）的电路变化，包括串联连接在电源电压（Vcc）和地之间的至少一个场效应晶体管（M1）和相关联的电阻偏置元件（R） （GND），还包括连接到第一晶体管的第二场效应晶体管（M2），使得可以拾取参考电压（Vref）作为两个晶体管的各个阈值电压之间的差。 这提供了对温度和工艺参数变化独特稳定的参考电压。
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6.发明授权
公开(公告)号：US5687124A
公开(公告)日：1997-11-11
申请号：US521304
申请日：1995-08-30
申请人： Carla Golla , Silvia Padoan , Luigi Pascucci
发明人： Carla Golla , Silvia Padoan , Luigi Pascucci
CPC分类号： G11C16/3486 , G11C16/3459 , G11C16/3468
摘要： A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.
摘要翻译： 公开了一种用于在非易失性存储器中选择性地编程单个位的电路。 电路由至少一个比较器，至少一个晶体管和至少一个逻辑门组成，用于存储器字中的每个基本存储器。 在操作中，电路允许通过将存储器的实际内容与期望的内容进行比较来对存储器内的错误编程的单元进行单独校正。 如果实际内容与所需内容不匹配，那么该单个单元格将被重新编程。
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公开(公告)号：US5724395A
公开(公告)日：1998-03-03
申请号：US188569
申请日：1994-01-28
申请人： Carla Golla , Alessandro Cremonesi
发明人： Carla Golla , Alessandro Cremonesi
CPC分类号： H03H17/0223
摘要： A method of filtering digital signals having a high dynamic range includes splitting the sampled input signal into at least two portions addressing each of the portions to a respective program filter, and performing each filtering operation in parallel and independently, and reconstituting an output signal by summing together the digital outputs from each filter.
摘要翻译： 一种对具有高动态范围的数字信号进行滤波的方法包括：将采样的输入信号分成至少两部分，将每个部分寻址到相应的节目滤波器，并且并行且独立地执行每个滤波操作，并通过求和来重构输出信号 将来自每个滤波器的数字输出组合在一起。
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公开(公告)号：US5594677A
公开(公告)日：1997-01-14
申请号：US189271
申请日：1994-01-28
申请人： Carla Golla , Alessandro Cremonesi
发明人： Carla Golla , Alessandro Cremonesi
CPC分类号： H03H17/0286 , H03H17/02 , H03H2017/0247
摘要： The input signal is filtered using at least two filtering operations (i.e. at least two types of transfer functions), and then is reconstituted by summing the two different digital outputs generated by each filtering arrangement, for example by using a summing circuit. In a preferred embodiment of the invention, a single programmable filter processor is used and is operated in two alternately selected modes, each sharing common filter coefficients. A clock signal alternately selects the two filtering modes. The subsequent outputs from a first mode are delayed and then added to the output of the second mode to produce the desired output signal.
摘要翻译： 使用至少两个滤波操作（即至少两种传递函数）对输入信号进行滤波，然后通过例如通过使用求和电路对由每个滤波装置产生的两个不同的数字输出相加来进行重构。 在本发明的优选实施例中，使用单个可编程滤波器处理器并且以两个交替选择的模式操作，每个模式共享共同的滤波器系数。 时钟信号交替选择两种滤波模式。 来自第一模式的后续输出被延迟，然后被添加到第二模式的输出以产生期望的输出信号。
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公开(公告)号：US5471413A
公开(公告)日：1995-11-28
申请号：US66567
申请日：1993-05-25
申请人： Luigi M. Sali , Carla Golla
发明人： Luigi M. Sali , Carla Golla
摘要： A fast adder chain for adding together at least one pair of digital words and including a plurality of cascade connected adder blocks. Each block including adders for obtaining the pseudosum of portions of the digital word pair and latches for storing and transmitting the pseudosum to the next block and the pseudocarry from each adder to the chain end.
摘要翻译： 一种用于将至少一对数字字相加并包括多个级联连接的加法器块的快速加法器链。 每个块包括用于获得数字字对的部分的伪距的加法器和用于存储并将伪随机数传送到下一个块的锁存器，以及从每个加法器到链末端的伪代码。
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公开(公告)号：US06055665A
公开(公告)日：2000-04-25
申请号：US816766
申请日：1997-03-18
申请人： Maurizio Branchetti , Armando Conci , Carla Golla
发明人： Maurizio Branchetti , Armando Conci , Carla Golla
IPC分类号： G06F11/10
CPC分类号： G06F11/1068
摘要： The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device set up as a multi-sector memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by selection circuitry, whenever the device fails an operation test. The use of a Hamming code for error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.
摘要翻译： 本发明涉及一种恢复故障非易失性存储器的方法。 该方法可以应用于设置为多扇区存储器矩阵的电可编程半导体非易失性存储器件，并且包括用于选择存储器的字或单个字节的选择电路。 根据这种方法，无论何时设备操作测试失败，存储器矩阵都由字节寻址，而不是由存储器字进行寻址。 使用汉明码进行错误纠正来纠正由于制造造成的故障，可以将该方法应用于那些未经测试的设备，否则将被视为拒绝。
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