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1.发明授权Voltage regulator for programming non-volatile and electrically programmable memory cells 失效用于编程非易失性和电可编程存储单元的电压调节器
公开(公告)号：US5519656A
公开(公告)日：1996-05-21
申请号：US366259
申请日：1994-12-29
申请人： Marco Maccarrone , Marco Olivo , Carla Golla , Silvia Padoan
发明人： Marco Maccarrone , Marco Olivo , Carla Golla , Silvia Padoan
摘要： A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.
摘要翻译： 一种用于编程非易失性存储单元的电压调节器，其包括在第一和第二参考电压之间供电的放大器级，并且具有连接到第一参考电压的电阻分压器的第一输入端和反馈到所述第一参考电压的输出端 通过电流镜输入，源极跟随器晶体管由输出端控制，并通过编程线与单元连接。 还提供了连接到编程线的接地的MOS晶体管和连接在电流镜与第二参考电压之间的相应的电阻路径。
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公开(公告)号：US5748548A
公开(公告)日：1998-05-05
申请号：US711132
申请日：1996-09-09
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.
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3.发明授权Regulation circuit and method for the erasing phase of non-volatile memory cells 失效非易失性存储单元擦除阶段的调节电路和方法
公开(公告)号：US5617356A
公开(公告)日：1997-04-01
申请号：US395361
申请日：1995-02-21
申请人： Carla Golla , Silvia Padoan , Marco Olivo
发明人： Carla Golla , Silvia Padoan , Marco Olivo
摘要： A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
摘要翻译： 一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关， 所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。 还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。 该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。
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公开(公告)号：US5583820A
公开(公告)日：1996-12-10
申请号：US366211
申请日：1994-12-29
申请人： Silvia Padoan , Marco Olivo , Carla Golla
发明人： Silvia Padoan , Marco Olivo , Carla Golla
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , G11C11/407
摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.
摘要翻译： 一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。 比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。 稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。 电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。
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公开(公告)号：US5600594A
公开(公告)日：1997-02-04
申请号：US412326
申请日：1995-03-31
申请人： Silvia Padoan , Marco Maccarrone , Marco Olivo
发明人： Silvia Padoan , Marco Maccarrone , Marco Olivo
CPC分类号： G11C29/50004 , G11C29/50 , G06F2201/81 , G11C16/04
摘要： A circuit device for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier having a first input connected to a first circuit leg including at least one memory cell and a second input connected to a second or reference circuit leg, and circuit means effective to cause an unbalance in the values of the currents flowing in the reference leg. The device is connected between a first supply voltage reference and a second voltage reference, and said circuit means comprise a generator of a varying current as a function of the supply voltage which is associated with the reference leg.
摘要翻译： 一种用于测量电可编程，非易失性存储单元之间的阈值电压分布的电路装置，该装置包括差分放大器，该差分放大器具有连接到包括至少一个存储单元的第一电路支路的第一输入端和连接到第二或 参考电路支路和电路装置有效地引起在参考支路中流动的电流值的不平衡。 该设备连接在第一电源参考电压和第二参考电压之间，并且所述电路装置包括作为与参考支路相关联的电源电压的函数的变化电流的发电机。
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公开(公告)号：US5627790A
公开(公告)日：1997-05-06
申请号：US408589
申请日：1995-03-22
申请人： Carla M. Golla , Marco Olivo , Silvia Padoan
发明人： Carla M. Golla , Marco Olivo , Silvia Padoan
摘要： A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.
摘要翻译： 一种包括通过选择电路连接到多个位线的负载的设备，以及连接到参考单元的负载，用于检测所选位线和参考单元中的电流。 连接到位线的负载包括晶体管，并且参考负载包括两个电流路径，每个由一个晶体管形成。 两个晶体管中的一个是二极管连接的，另一个晶体管可以由连接到相应晶体管的栅极端子的开关网络切换，以便在仅使能一个参考电流路径时将其关断，并且用于二极管连接 当两个参考电流路径都要使能时。
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7.发明授权Circuit device and corresponding method for resetting non-volatile and electrically programmable memory devices 失效用于复位非易失性和电可编程存储器件的电路器件和相应的方法
公开(公告)号：US5586077A
公开(公告)日：1996-12-17
申请号：US366212
申请日：1994-12-29
申请人： Marco Olivo , Silvia Padoan
发明人： Marco Olivo , Silvia Padoan
CPC分类号： G11C16/30
摘要： A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a supply voltage and a programming voltage, and a threshold detection circuit adapted to detect a decrease in the supply voltage, provides for the signal applied to the control logic to be obtained as a change-over function between the output signal from the threshold detector and a reset signal generated during the power-on transient of the device.
摘要翻译： 一种用于在电可编程非易失性存储装置中产生复位信号的方法，该方法包括存储单元矩阵和提供电源电压和编程电压的控制逻辑部分，以及阈值检测电路， 降低电源电压，提供作为在来自阈值检测器的输出信号与在器件的上电瞬变期间产生的复位信号之间的转换功能而获得的控制逻辑的信号。
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公开(公告)号：US5532972A
公开(公告)日：1996-07-02
申请号：US391920
申请日：1995-02-21
申请人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Silvia Padoan , Carla M. Golla , Marco Maccarrone , Marco Olivo
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.
摘要翻译： 电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播 输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。
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公开(公告)号：US5687135A
公开(公告)日：1997-11-11
申请号：US700126
申请日：1996-08-20
申请人： Marco Olivo , Marco Maccarrone
发明人： Marco Olivo , Marco Maccarrone
摘要： A count unit for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter and a number of registers equal in number to the count functions involved. The registers store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One of the registers presents a second parallel input for externally loading an initial data which may be transferred to the other registers via the counter.
摘要翻译： 用于执行多个计数操作的计数单元，并且其中，代替每个计数功能的计数器，提供一个计数器和与所涉及的计数功能相等数量的寄存器数量。 寄存器存储上述计数值，当其内容要增加或以任何方式更改时，将其加载到计数器中，该计数器用于执行所需的操作，最后计数器的内容存储在 各自的登记册。 其中一个寄存器提供第二个并行输入，用于外部加载初始数据，初始数据可以通过计数器传输到其他寄存器。
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10.发明授权Method and circuit for suppressing data loading noise in nonvolatile memories 失效用于抑制非易失性存储器中的数据加载噪声的方法和电路
公开(公告)号：US5541884A
公开(公告)日：1996-07-30
申请号：US391147
申请日：1995-02-21
申请人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone , Marco Olivo
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.
摘要翻译： 在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到 输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。 相同的信号也阻塞地址总线上的地址放大单元。
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