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    Data processing apparatus with parallel operating functional units
    1.
    发明申请
    Data processing apparatus with parallel operating functional units 有权
    具有并行运行功能单元的数据处理装置

    公开(公告)号：US20050273569A1

    公开(公告)日：2005-12-08

    申请号：US10530375

    申请日：2003-09-17

    申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

    发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  harm Johannes Peters ,  Rafael Peset Llopis

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/00

    CPC分类号： G06F9/3802 ,  G06F9/3853

    摘要： A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

    摘要翻译： 用VLIW数据处理装置执行指令字的程序。 该装置包括能够并行地从每个指令字执行多个指令的多个功能单元。 来自各个指令字中的至少一些的指令被并行地从相应的存储器单元中取出，用功能单元共用的指令地址寻址。 将指令地址转换为物理地址可以针对一个或多个特定存储器单元进行修改。 修改由程序中的修改更新指令控制。 因此，可以根据程序执行来选择来自存储器单元的指令将响应于指令地址而组合到指令字中。

    Vl1w processor with power saving
    3.
    发明申请
    Vl1w processor with power saving 有权
    Vl1w处理器省电

    公开(公告)号：US20060156004A1

    公开(公告)日：2006-07-13

    申请号：US10530639

    申请日：2003-09-17

    申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

    发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

    IPC分类号： H04N17/00

    CPC分类号： G06F9/3853 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30167 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

    摘要翻译： 数据处理装置具有指令存储器系统，其被布置为输出能够包含多个指令的指令字，响应于相应的指令地址输出相应的指令字。 指令执行单元包含多个功能单元，每个功能单元能够执行来自指令字的相应指令，并且与其他功能单元从指令字执行其他指令并行执行。 提供省电电路以将功能单元和/或指令存储器的可选择子集切换到省电状态，而指令存储器的其他功能单元和部分在正常功耗状态下继续处理指令。 省电电路根据程序执行选择指令存储器的功能单元和/或部分。

    DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS
    4.
    发明申请
    DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS 审中-公开
    数据处理设备地址范围依赖于指令的并行

    公开(公告)号：US20130138927A1

    公开(公告)日：2013-05-30

    申请号：US13751324

    申请日：2013-01-28

    申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

    发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

    摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

    摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

    Very long instruction word processor
    5.
    发明申请
    Very long instruction word processor 审中-公开
    很长的指令字处理器

    公开(公告)号：US20060095715A1

    公开(公告)日：2006-05-04

    申请号：US10540698

    申请日：2003-12-03

    申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto ,  Harm Johannes Peters

    发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto ,  Harm Johannes Peters

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3885 ,  G06F9/3853

    摘要： The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). The VLIW processor comprises at least one indication means (140) associated with one of said functional units (135) and adapted to registering and indicating to the VLIW controller (100) whether said one functional unit (135) is idle or operating.

    摘要翻译： 本发明涉及一种非常长的指令字（VLIW）处理器，它包括多个用于执行操作的功能单元（110,130,135），和连接到每个所述功能单元（110,130,135）的VLIW控制器（100） 130,135），并适于控制所述功能单元（110,130,135）。 所述VLIW处理器包括与所述功能单元（135）之一相关联的至少一个指示装置（140），并且适于向VLIW控制器（100）注册和指示所述一个功能单元（135）是空闲还是操作。

    Data processing apparatus address range dependent parallelization of instructions
    6.
    发明授权
    Data processing apparatus address range dependent parallelization of instructions 有权
    数据处理装置地址范围依赖于指令的并行化

    公开(公告)号：US08364935B2

    公开(公告)日：2013-01-29

    申请号：US10530495

    申请日：2003-10-01

    申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

    发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Rafael Peset Llopis

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

    摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

    摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。

    Pipelined instruction processor with data bypassing
    8.
    发明申请
    Pipelined instruction processor with data bypassing 有权
    流水线指令处理器，数据旁路

    公开(公告)号：US20060212686A1

    公开(公告)日：2006-09-21

    申请号：US10549368

    申请日：2004-03-17

    申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto

    发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto

    IPC分类号： G06F9/44

    CPC分类号： G06F8/445 ,  G06F9/30141 ,  G06F9/3826 ,  G06F9/3859 ,  G06F9/3865 ,  G06F9/3869

    摘要： An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to control of the instructions.

    摘要翻译： 指令处理装置具有管线级，其具有用于从指令执行命令的功能单元。 第一寄存器单元耦合到功能单元，用于当命令已经到达第一个流水线级时存储命令的执行结果，并且用于将旁路操作数数据提供给功能单元。 寄存器文件耦合到功能单元，用于当命令已经到达第一个流水线级的第一个流水线级的下游，并且将操作数数据提供给功能单元时存储结果。 禁用电路耦合到控制指令。

    Pipelined instruction processor with data bypassing and disabling circuit
    9.
    发明授权
    Pipelined instruction processor with data bypassing and disabling circuit 有权
    带数据旁路和禁用电路的流水线指令处理器

    公开(公告)号：US07730284B2

    公开(公告)日：2010-06-01

    申请号：US10549368

    申请日：2004-03-17

    申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Antonio Alba Pinto

    发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Antonio Alba Pinto

    IPC分类号： G06F9/30

    CPC分类号： G06F8/445 ,  G06F9/30141 ,  G06F9/3826 ,  G06F9/3859 ,  G06F9/3865 ,  G06F9/3869

    摘要： An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.

    摘要翻译： 指令处理装置具有管线级，其具有用于从指令执行命令的功能单元。 第一寄存器单元耦合到功能单元，用于当命令已经到达第一个流水线级时存储命令的执行结果，并且用于将旁路操作数数据提供给功能单元。 寄存器文件耦合到功能单元，用于当命令已经到达第一个流水线级的第一个流水线级的下游，并且将操作数数据提供给功能单元时存储结果。 耦合禁止电路以在指令的控制下选择性地禁止将结果存储在寄存器文件中。

    Instruction Controlled Data Processing Device
    10.
    发明申请
    Instruction Controlled Data Processing Device 有权
    指令控制数据处理装置

    公开(公告)号：US20080133880A1

    公开(公告)日：2008-06-05

    申请号：US10561454

    申请日：2004-06-22

    申请人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

    发明人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F9/3826 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152

    摘要： The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

    摘要翻译： 数据处理装置具有多个功能单元并在连续的指令周期中发出指令。 第一种类型的说明每次都用于一个功能单元。 第二类型的指令使得功能单元的组合在相同的指令执行周期中作出响应，这是由另一个功能单元作为执行相同指令的一部分使用的结果。 优选地，该设备支持多个不同指令周期速率的替代操作，取决于所执行的程序段是否包含第二类型的指令。 最快的指令周期速率不允许执行第二种指令，因为不同功能单元的操作不符合指令执行周期。 如果可能，设备通过切换到较慢的时钟速率来节省功率，在这种情况下，通过减少必须发出的指令数量来执行第二种类型的指令以节省额外的功率。