Method for manufacturing a calibration device
    1.
    发明授权
    Method for manufacturing a calibration device 失效
    校准装置的制造方法

    公开(公告)号:US07698802B2

    公开(公告)日:2010-04-20

    申请号:US12028439

    申请日:2008-02-08

    IPC分类号: G01R31/28

    摘要: A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.

    摘要翻译: 一种用于制造芯片上的有源电路的校准装置的方法,包括:提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。 所述校准机构产生控制输出,并且包括被配置为所述有源电路的至少一个段的复制品的被测器件(DUT),并且基于所述被测器件的比较,产生对所述控制输出进行有限调整的测试输出 具有已知电特性的DUT所呈现的电特性。 该方法还包括:将有源电路的每个控制输入端连接到校准机构的相应控制输出。 校准机构的控制输出动态调整施加到有源电路的器件的控制输入,以迫使有源电路呈现所需的电特性。

    Impedance calibration for source series terminated serial link transmitter
    2.
    发明授权
    Impedance calibration for source series terminated serial link transmitter 有权
    源串联端接串行链路发射机的阻抗校准

    公开(公告)号:US07368902B2

    公开(公告)日:2008-05-06

    申请号:US11262101

    申请日:2005-10-28

    摘要: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

    摘要翻译: 将被测器件(DUT)的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接(SST)串行链路发射机的一部分,其中当并联支路的特定晶体管导通时,并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较,并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM(有限状态机)进行处理,FSM单独打开或关闭并联支路内的晶体管,直到DUT阻抗值落在所需范围内。

    Impedance calibration for source series terminated serial link transmitter
    3.
    发明授权
    Impedance calibration for source series terminated serial link transmitter 失效
    源串联端接串行链路发射机的阻抗校准

    公开(公告)号:US07570071B2

    公开(公告)日:2009-08-04

    申请号:US12028451

    申请日:2008-02-08

    摘要: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

    摘要翻译: 将被测器件(DUT)的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接(SST)串行链路发射机的一部分,其中当并联支路的特定晶体管导通时,并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较,并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM(有限状态机)进行处理,FSM单独打开或关闭并联支路内的晶体管,直到DUT阻抗值落在所需范围内。

    Impedance Calibration for Source Series Terminated Serial Link Transmitter
    4.
    发明申请
    Impedance Calibration for Source Series Terminated Serial Link Transmitter 失效
    源串联终端串行链路发射机的阻抗校准

    公开(公告)号:US20080120838A1

    公开(公告)日:2008-05-29

    申请号:US12028439

    申请日:2008-02-08

    IPC分类号: H01R43/00

    摘要: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

    摘要翻译: 将被测器件(DUT)的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接(SST)串行链路发射机的一部分,其中当并联支路的特定晶体管导通时,并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较,并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM(有限状态机)进行处理,FSM单独打开或关闭并联支路内的晶体管,直到DUT阻抗值落在所需范围内。

    One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery
    6.
    发明授权
    One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
    单采样每位决策反馈均衡器(DFE)时钟和数据恢复

    公开(公告)号:US07809054B2

    公开(公告)日:2010-10-05

    申请号:US11405997

    申请日:2006-04-18

    IPC分类号: H03H7/30 H03H7/40 H03K5/159

    CPC分类号: H04L25/03063

    摘要: Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

    摘要翻译: 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器(DFE)时钟和数据恢复(CDR)架构的接收器电路,方法和设计架构,并且降低了误码率(BER )。 集成接收机与决策反馈均衡器以及适当的(CDR)环路相位检测器相结合,以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外,总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后,积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

    Using statistical signatures for testing high-speed circuits
    7.
    发明授权
    Using statistical signatures for testing high-speed circuits 失效
    使用统计特征来测试高速电路

    公开(公告)号:US07661052B2

    公开(公告)日:2010-02-09

    申请号:US12021950

    申请日:2008-01-29

    IPC分类号: G06F11/277 G06F11/16

    CPC分类号: G01R31/31901 G01R31/31707

    摘要: A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.

    摘要翻译: 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此,可以确定高速电路是否在期望的参数内起作用。

    method for providing automatic adaptation to frequency offsets in high speed serial links
    8.
    发明授权
    method for providing automatic adaptation to frequency offsets in high speed serial links 有权
    用于在高速串行链路中提供自动适应频率偏移的方法

    公开(公告)号:US07477713B2

    公开(公告)日:2009-01-13

    申请号:US10791175

    申请日:2004-03-02

    IPC分类号: H04L7/02

    摘要: Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

    摘要翻译: 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号,第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器,用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。

    Method and system for data and edge detection with correlation tables
    9.
    发明授权
    Method and system for data and edge detection with correlation tables 有权
    具有相关表的数据和边缘检测方法和系统

    公开(公告)号:US07349498B2

    公开(公告)日:2008-03-25

    申请号:US10265981

    申请日:2002-10-07

    IPC分类号: H04L27/06 H03D27/06

    CPC分类号: H04L7/0338 H03K5/1534

    摘要: A system and method is disclosed for evaluating a data group of oversampled bits to detect edge transitions and for improving use of information available from a sampled data while maintaining acceptable noise rejection. An edge detection system for receiving a serial data stream includes a sampler for collecting a sample pattern from the serial data stream, the sample pattern including a succession of a plurality of data samples from the data stream with the plurality of data samples including multiple samples during a bit time associated with the data stream; a memory, coupled to the sampler, for storing one or more successive sample patterns; and a correlator, coupled to the memory, for producing a sample condition signal using a set of predefined patterns by comparing the stored sampled patterns to the predefined patterns.

    摘要翻译: 公开了一种系统和方法,用于评估过采样比特的数据组以检测边缘转换并改善对采样数据可用信息的使用,同时保持可接受的噪声抑制。 用于接收串行数据流的边缘检测系统包括:采样器,用于从串行数据流收集采样模式,样本模式包括来自数据流的多个数据样本的一系列,其中多个数据样本包括多个样本 与数据流相关联的一段时间; 耦合到采样器的存储器,用于存储一个或多个连续的采样图案; 以及耦合到存储器的相关器,用于通过将所存储的采样图案与预定义图案进行比较,使用一组预定义图案来产生采样条件信号。

    Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery
    10.
    发明授权
    Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery 失效
    用于时钟和数据恢复的接收器以及用于校准接收机中的采样相位以用于时钟和数据恢复的方法

    公开(公告)号:US07149269B2

    公开(公告)日:2006-12-12

    申请号:US10375286

    申请日:2003-02-27

    IPC分类号: H03D3/24

    摘要: A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).

    摘要翻译: 用于时钟和数据恢复的接收机包括n个采样锁存器(SL1 ... SLn),用于确定n个采样相位(参见图1a)上的参考信号(Ref 2)的n个采样值(SV1 ... SVn)。 (phina)具有采样锁存输入和采样锁存输出,接收器还包括连接到采样锁存器输出的相位位置分析器(5),用于产生调整信号(AS),用于调整采样相位(phi 1 a。 如果采样值(SV1 ... SVn)偏离设定点,则产生采样相位(phi 1 u。。phinu)的相位插值器(9),连接的采样相位调整单元(6) 其相位位置分析器(5)和相位插值器(9)的输入及其对采样锁存器(SL1 ... SLn)的输出被提供用于产生经调整的采样相位(phi1,...) 取决于采样相位(phi 1 u。。phinu)和所述调整信号(AS)。