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公开(公告)号：US5120996A
公开(公告)日：1992-06-09
申请号：US535283
申请日：1990-06-06
CPC分类号： G11C27/024 , G06N3/063 , G11C11/54
摘要： An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic cicuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed.
摘要翻译： 公开了一种具有连接到自适应放大器的采样/保持放大器的电子电路。 多个这样的电子线路可以被配置成行和列的阵列。 可以将输入电压矢量与存储在阵列的行或列中的模拟电压矢量进行比较，并且可以识别并进一步处理最接近所施加的输入向量的存储向量。
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公开(公告)号：US5083044A
公开(公告)日：1992-01-21
申请号：US357520
申请日：1989-05-25
摘要： An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed.
摘要翻译： 公开了一种具有连接到自适应放大器的采样/保持放大器的电子电路。 多个这样的电子电路可以被配置成行和列的阵列。 可以将输入电压矢量与存储在阵列的行或列中的模拟电压矢量进行比较，并且可以识别并进一步处理最接近所施加的输入向量的存储向量。
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公开(公告)号：US5331215A
公开(公告)日：1994-07-19
申请号：US922535
申请日：1992-07-30
申请人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
发明人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.
摘要翻译： 根据本发明的突触阵列包括多个电适应元件。 可以通过施加产生的第一和第二电控制信号将电子放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的每个电适应元件中的浮动节点上并从其移除， 响应于适配信号。 对一行中所有突触元素的输入连接到公共行输入行。 将输入到列中的所有突触元素的调整连接到公共列适应线。 提供给列中所有放大器的电流通常由感测线提供。 为了适应本发明的M行×N列矩阵中的突触元素，要将矩阵的给定列n适应的电压放置在输入电压线上，并且列n中的突触元素 然后通过在第n列的适应线上断言适配信号同时进行调整。 用于适配连续列的输入电压的矢量可以顺序地放置在行输入电压线上，并且用于通过在适当的列适配线上断言适配信号来适应突触元件的列，直到整个阵列电气适配。 在每个突触元件已经适应之后，当突触元件的输入端的电压等于突触元件适应的电压时，流过它的电流将被最大化。 电气适应性的胜者总线电路的输入连接到阵列的列感测线。
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公开(公告)号：US5166562A
公开(公告)日：1992-11-24
申请号：US697410
申请日：1991-05-09
CPC分类号： G05F1/468 , G05F3/24 , G11C11/56 , G11C11/5621 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.
摘要翻译： 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 跟随放大器连接到每个浮动栅极存储装置并驱动模拟输出电压总线。 电容器连接到每个模拟输出存储总线。 每个模拟输出电压总线和公共监视器/动态负载总线之间连接一个模拟传输门。 每个模拟传输门由选通信号驱动。
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公开(公告)号：US5160899A
公开(公告)日：1992-11-03
申请号：US781503
申请日：1991-10-22
CPC分类号： G06N3/063 , H01L27/0629 , H03F1/0261 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.
摘要翻译： 适应电流镜包括第一和第二MOS晶体管。 第一个MOS晶体管的栅极连接到其漏极。 MOS电容器结构串联连接在第一MOS晶体管的栅极和第二MOS晶体管的栅极之间。 电子可以通过施加第一和第二电气控制信号，以模拟方式从与第二MOS晶体管（通常是晶体管的栅极）相关联的浮动节点放置和去除。 第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。 可以采用与多个载流线路通信的多个适应电流镜，以指示最流动的多个通电线路中的一个的输出。
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公开(公告)号：US5243554A
公开(公告)日：1993-09-07
申请号：US961785
申请日：1992-10-15
CPC分类号： G11C11/5621 , G05F1/468 , G05F3/24 , G11C11/56 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.
摘要翻译： 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 跟随放大器连接到每个浮动栅极存储装置并驱动模拟输出电压总线。 电容器连接到每个模拟输出存储总线。 每个模拟输出电压总线和公共监视器/动态负载总线之间连接一个模拟传输门。 每个模拟传输门由选通信号驱动。
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公开(公告)号：US5119038A
公开(公告)日：1992-06-02
申请号：US650577
申请日：1991-02-04
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.
摘要翻译： MOS电流镜包括浮动节点，在该浮动节点上，可以通过控制信号和电半导体结构从中传输电子，以便在存在特定输入校准电流时使电流镜适应于提供期望的输出电流。
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公开(公告)号：US5146106A
公开(公告)日：1992-09-08
申请号：US650959
申请日：1991-02-05
CPC分类号： H01L27/0629 , G06N3/063 , H03F1/0261 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.
摘要翻译： 可适应的MOS优胜者采取所有电路包括多个适应电流镜。 每个可适应电流镜包括浮动节点，电子可以通过控制信号和电半导体结构传输到该浮动节点上。 通过施加第一和第二电控制信号，电子可以以模拟的方式放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。 第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。
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公开(公告)号：US5059920A
公开(公告)日：1991-10-22
申请号：US525764
申请日：1990-05-18
CPC分类号： H03F1/0261 , G06N3/063 , H01L27/0629 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.
摘要翻译： 通过施加第一和第二电气控制信号，电子可以以模拟方式放置在与至少一个MOS晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。 第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。 模拟MOS集成电路包括具有大于1的增益的放大器电路。该放大器电路的一级的反相输入是形成至少一个MOS晶体管的栅极的浮动节点。 第一个电容将电路的输入耦合到该浮动节点。 提供电气半导体结构用于从浮动栅极线性地添加和去除电荷，从而允许放大器的偏移电压被适配。 具有随机输入偏移电压的集成电路放大器是可适应的，使得可以抵消输入偏移电压。 反相输入节点是浮动输入节点，并通过第一电容器耦合到输入信号源。 第二电容器连接在放大器的输出端和浮动节点之间。 电学习装置允许浮动节点被充电或放电到有效地抵消输入偏移电压的电压。
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公开(公告)号：US4962342A
公开(公告)日：1990-10-09
申请号：US347837
申请日：1989-05-04
CPC分类号： G11C27/026 , G06N3/063 , G06N3/0635
摘要： An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed. The stored analog value may be read out of the synapse by applying a voltage to a read line. An array of the readable synapses may be provided and used in conjunction with a dummy synapse to compensate for an error offset introduced by the operating characteristics of the synapses.
摘要翻译： 公开了一种具有连接到自适应放大器的采样/保持放大器的电子电路。 多个这样的电子电路可以被配置成行和列的阵列。 可以将输入电压矢量与存储在阵列的行或列中的模拟电压矢量进行比较，并且可以识别并进一步处理最接近所施加的输入向量的存储向量。 存储的模拟值可以通过向读取线施加电压而从突触中读出。 可以提供可读突触的阵列并结合虚拟突触使用以补偿由突触的操作特征引入的误差偏移。
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