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    Mechanism for accessing multiple virtual address spaces
    3.
    发明授权
    Mechanism for accessing multiple virtual address spaces 失效

    公开(公告)号：US4521846A

    公开(公告)日：1985-06-04

    申请号：US236387

    申请日：1981-02-20

    申请人： Casper A. Scalzi ,  Richard J. Schmalz

    发明人： Casper A. Scalzi ,  Richard J. Schmalz

    IPC分类号： G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F13/00

    CPC分类号： G06F12/0292

    摘要： The disclosure provides a general purpose register (GR) mask which associates predesignated address spaces with respective GRs assigned to contain a base value for calculating logical addresses within the address spaces. An address space mask register has a plurality of digit positions which receive the respective digit values comprising a particular GR mask. A respective digit position is selected by a base GR address signal provided by a storage address request from a CPU instruction decoder. The particular value of the selected digit in the mask register controls the selection among a plurality of STO registers, which designate a plurality of simultaneously available address spaces. The selected base GR is used in a System/370 B, D or X, B, D type of logical storage address representation. A base GR explicitly contains an intra-address-space base value. The GR mask assigns an implicit inter-address-space designation to the base GR in a simple manner which is handled by conventional address translation hardware. The available address spaces are respectively designated in STO registers by segment table addresses (called STOs). Any number of STO registers (and available address spaces) may be provided up to the radix of each digit in the GR mask. The executing program exists in the address space designated in one of the STO registers. A plurality of storage protect key registers are respectively associated with the STO registers to control the accessing authorized to the executing program within each available address space. The key value may be independently authorized and provided for each available address space. A cross-memory implementation results which enables a compatible extension of the IBM System/370 architecture by permitting the unrestricted use of all S/370 instructions including storage-to-storage (SS) instructions that can access data simultaneously in plural address spaces in non-privileged state.

    Address generating mechanism for multiple virtual spaces
    4.
    发明授权
    Address generating mechanism for multiple virtual spaces 失效
    多个虚拟空间的地址生成机制

    公开(公告)号：US4355355A

    公开(公告)日：1982-10-19

    申请号：US131570

    申请日：1980-03-19

    申请人： Justin R. Butwell ,  Casper A. Scalzi ,  Richard J. Schmalz

    发明人： Justin R. Butwell ,  Casper A. Scalzi ,  Richard J. Schmalz

    IPC分类号： G06F9/34 ,  G06F12/06 ,  G06F12/10 ,  G06F12/14 ,  G06F9/36

    CPC分类号： G06F12/1475 ,  G06F12/0623 ,  G06F12/1036

    摘要： The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The invention allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data.The embodiment obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.

    摘要翻译： 详细实施例将访问寄存器（AR）与通用寄存器（GPR）在数据处理器中相关联。 每个AR都加载了一个唯一的STD（段表描述符）。 STD包括主存储器中的段表地址和段表长度字段。 在处理器中有15个AR分别与15个GPR相关联，以定义多达15个数据地址空间的子集。 当选择相关联的GPR作为存储操作数基址寄存器时，AR中的STD被选择用于地址转换，例如由IBM System / 370指令中的B字段选择的GPR。 本发明允许每个AR指定它不使用其关联的AR中的STD来定义其数据地址空间，而是在程序地址空间AR中使用STD。 然而，如果相关联的GPR被选择用于除了作为存储操作数的基本寄存器之外的目的，例如如果选择GPR作为索引（X）寄存器或者作为索引（X）寄存器，则不选择AR的STD内容用于地址转换 用于指令的数据源或接收寄存器（R）。 可以提供第十六AR以定义和控制也可以包含数据的执行程序地址空间。 该实施例还通过将AR控制向量（ARCV）寄存器与每个AR相关联来获得对每个地址空间中的内容的访问和使用的权限和其他控制。

    Dynamic program analyzer facility
    6.
    发明授权
    Dynamic program analyzer facility 失效
    动态程序分析仪设备

    公开(公告)号：US5454086A

    公开(公告)日：1995-09-26

    申请号：US928937

    申请日：1992-08-11

    申请人： Alan I. Alpert ,  Carl E. Clark ,  Michel H. T. Hack ,  Casper A. Scalzi ,  Richard J. Schmalz, deceased ,  Bhaskar Sinha

    发明人： Alan I. Alpert ,  Carl E. Clark ,  Michel H. T. Hack ,  Casper A. Scalzi ,  Richard J. Schmalz, deceased ,  Bhaskar Sinha

    IPC分类号： G06F11/28 ,  G06F9/40 ,  G06F11/36 ,  G06F9/00 ,  G06F11/00

    CPC分类号： G06F11/3636 ,  G06F9/4425

    摘要： Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction. One or more hooked programs may concurrently use the same analyzer program. As soon as execution by the analyzer program ends for a hook instruction, its assigned HWA is released for use by another hook instruction.

    摘要翻译： 在分析程序与程序中的每个挂钩指令之间提供动态执行链接。 提供特殊类型的挂钩指令用于挂钩程序。 该链接使分析程序作为每个挂钩指令的连续不间断执行的一部分执行。 该链接使用硬件和/或内部代码访问挂钩控制区域，其提供在完成钩指令时调用分析器程序的执行所需的链接信息，并且在分析器程序完成之后继续执行挂钩程序 。 链接信息包括进入分析器程序的入口位置，并且还定位HWAs序列的第一挂钩工作区域（HWA），HWA被分配给每个当前挂钩指令。 所分配的HWA在当前挂钩指令之后的指令处在挂钩程序中存储返回点位置。 一个或多个挂钩程序可以同时使用相同的分析程序。 一旦分析程序的执行结束为​​一个挂接指令，其分配的HWA被释放供另一个钩子指令使用。

    Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media
    7.
    发明授权
    Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media 失效
    在非特权指令中使用虚拟寻址来控制数据在多媒体之间或之间复制的过程

    公开(公告)号：US5237668A

    公开(公告)日：1993-08-17

    申请号：US424797

    申请日：1989-10-20

    申请人： Geoffrey O. Blandy ,  David B. Emmes ,  Ronald F. Hill ,  David B. Lindquist ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

    发明人： Geoffrey O. Blandy ,  David B. Emmes ,  Ronald F. Hill ,  David B. Lindquist ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz

    IPC分类号： G06F12/10 ,  G06F12/14

    CPC分类号： G06F12/10 ,  G06F12/145

    摘要： A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory program when each medium and the virtual addresses are previously determined. The instruction is not required to specify which medium it will use, does not require its user to know what backing medium it will access, does not require main storage (MS) to be its backing medium, and allows different types of physical addressing to be used by different media. The instruction can lock any page for use in a multi-processor (MP). No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-MS medium page whether it is unlocked or locked, either correctly or incorrectly.

    Control mechanism for zero-origin data spaces
    9.
    发明授权
    Control mechanism for zero-origin data spaces 失效
    零原始数据空间的控制机制

    公开(公告)号：US5008811A

    公开(公告)日：1991-04-16

    申请号：US154688

    申请日：1988-02-10

    申请人： Casper A. Scalzi ,  Richard J. Schmalz

    发明人： Casper A. Scalzi ,  Richard J. Schmalz

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/14

    CPC分类号： G06F12/1475 ,  G06F12/1036

    摘要： Within a data processing system, a control mechanism for supporting a data space without common segments in addition to traditional address spaces containing common segments. Logic for eliminating duplication of lookaside table entries for virtual addresses within shared segments, but not for identical virtual addresses within data address spaces is provided, as well as for overriding low address protection for store operations into data spaces. Thus, the entire virtual addressing range is available to programs wishing to use such data spaces for data isolation and data sharing.

    Large logical addressing method and means
    10.
    发明授权
    Large logical addressing method and means 失效
    大逻辑寻址方式和手段

    公开(公告)号：US5381537A

    公开(公告)日：1995-01-10

    申请号：US803320

    申请日：1991-12-06

    申请人： Richard I. Baum ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Bhaskar Sinha

    发明人： Richard I. Baum ,  Kenneth E. Plambeck ,  Casper A. Scalzi ,  Richard J. Schmalz ,  Bhaskar Sinha

    IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/00

    CPC分类号： G06F12/0292

    摘要： A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results. An offset value of ALEs can be utilized to generate an effective ADEN and ALEN, which are utilized for the address translation of the LVA.

    摘要翻译： 当动态地址转换（DAT）模式打开时用于将大的逻辑地址翻译为大的虚拟地址（LVA）的方法和装置。 每个LVA被分成三个级联部分：1.用于索引到访问目录（AD）的最高阶部分（ADEN），以定位用于定位一个访问列表（AL）的条目（ADE）; 2.一种用于索引到所选择的AL以访问条目（ALE）的中间部分（ALEN），所述入口（ALE）使得能够定位表示常规大小的虚拟地址空间的相关联的常规地址转换表; 和3.具有与常规类型的虚拟地址相同大小的低阶DAT虚拟地址（VA）部分。 低阶DAT VA部分由相关联的常规地址转换表转换。 如果在创建低阶DAT VA部分期间产生进位信号，则会产生ALE选择的变化。 ALE的偏移值可用于生成有效的ADEN和ALEN，用于LVA的地址转换。