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公开(公告)号：US20190215142A1
公开(公告)日：2019-07-11
申请号：US16352180
申请日：2019-03-13
申请人： Cavium, LLC
发明人： Scott E. Meninger
IPC分类号： H04L7/00 , H04L1/00 , H03L7/08 , H03L7/00 , H04L27/227
CPC分类号： H04L7/0008 , G06F1/06 , G06F1/10 , H03L7/00 , H03L7/08 , H03L7/1976 , H03L7/23 , H03M9/00 , H04J3/0685 , H04L1/0065 , H04L27/2272
摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
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公开(公告)号：US20190182022A1
公开(公告)日：2019-06-13
申请号：US16281822
申请日：2019-02-21
申请人： Cavium, LLC
发明人： Lu Wang , Scott E. Meninger
IPC分类号： H04L5/22
CPC分类号： H04L5/22 , H04L25/02 , H04L25/0272
摘要： In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.
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公开(公告)号：US20190103956A1
公开(公告)日：2019-04-04
申请号：US15721334
申请日：2017-09-29
申请人： Cavium, LLC
发明人： Scott E. Meninger
IPC分类号： H04L7/00 , H04L1/00 , H04L27/227
摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
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公开(公告)号：US10461917B2
公开(公告)日：2019-10-29
申请号：US16352180
申请日：2019-03-13
申请人： Cavium, LLC
发明人： Scott E. Meninger
IPC分类号： H04L7/00 , H03L7/00 , H03L7/08 , H04L27/227 , H04L1/00
摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
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公开(公告)号：US20190214997A1
公开(公告)日：2019-07-11
申请号：US16165577
申请日：2018-10-19
申请人： Cavium, LLC
发明人： Scott E. Meninger , Ethan Crain , Mark Spaeth
CPC分类号： H03L7/0807 , H03L7/0812 , H03L7/085 , H03L7/0891
摘要： A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.
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公开(公告)号：US10291386B2
公开(公告)日：2019-05-14
申请号：US15721334
申请日：2017-09-29
申请人： Cavium, LLC
发明人： Scott E. Meninger
IPC分类号： H03L7/00 , H03L7/08 , H04L7/00 , H04L27/227 , H04L1/00
摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
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7.发明申请公开(公告)号：US20190165731A1
公开(公告)日：2019-05-30
申请号：US15825942
申请日：2017-11-29
申请人： Cavium, LLC
摘要： A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal frequency band from a group of frequency bands including the initial frequency band selection, a higher frequency band consecutively higher in frequency relative to the initial frequency band selection, and a lower frequency band consecutively lower in frequency relative to the initial frequency band selection.
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公开(公告)号：US10263759B2
公开(公告)日：2019-04-16
申请号：US15497356
申请日：2017-04-26
申请人： Cavium, LLC
发明人： Lu Wang , Scott E. Meninger
摘要： In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.
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公开(公告)号：US20200007305A1
公开(公告)日：2020-01-02
申请号：US16569445
申请日：2019-09-12
申请人： Cavium, LLC
发明人： Scott E. Meninger
IPC分类号： H04L7/00 , H03L7/00 , H03L7/08 , H04L1/00 , H04L27/227
摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
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