公开(公告)号：US5985767A

公开(公告)日：1999-11-16

申请号：US228725

申请日：1999-01-12

申请人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L21/76844 ,  H01L2924/0002

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

摘要翻译： 公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。 在接触开口形成之前或之后，在绝缘层上沉积导电层。 在导电层沉积和接触形成之后，进行小面蚀刻以使覆盖接触唇的导电层倾斜，同时将材料从导电层沉积到接触的下角，其中覆盖传统上较差。 然后可以将第二导电层沉积到接触中以补充由第一导电层提供的覆盖层和小面蚀刻。

公开(公告)号：US5861344A

公开(公告)日：1999-01-19

申请号：US958655

申请日：1997-10-27

申请人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L21/76844 ,  H01L2924/0002

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

公开(公告)号：US5730835A

公开(公告)日：1998-03-24

申请号：US594842

申请日：1996-01-31

申请人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Ceredig Roberts ,  Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/00 ,  C23F1/00

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L21/76844 ,  H01L2924/0002

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

公开(公告)号：US5963832A

公开(公告)日：1999-10-05

申请号：US184489

申请日：1998-11-02

申请人： Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/285

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

公开(公告)号：US06423626B1

公开(公告)日：2002-07-23

申请号：US09334753

申请日：1999-06-16

申请人： Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76865 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

摘要翻译： 公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。 在接触开口形成之前或之后，在绝缘层上沉积初始导电层。 沉积过程倾向于以金属悬垂或尖端阻塞接触嘴。 在导电层沉积和接触形成两者之后，去除初始导电层的一部分，从而去除金属尖端的至少一部分并打开接触口以进一步沉积。 本发明在高纵横比触点形成金属插头方面具有特殊的用途。 公开了其中尖端去除包括机械平面化，用高粘度化学品蚀刻和小面蚀刻的实施例。

公开(公告)号：US5929526A

公开(公告)日：1999-07-27

申请号：US870105

申请日：1997-06-05

申请人： Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

发明人： Anand Srinivasan ,  Gurtej Sandhu ,  Sujit Sharan

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002

摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

公开(公告)号：US06800517B2

公开(公告)日：2004-10-05

申请号：US10792532

申请日：2004-03-02

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

公开(公告)号：US06750089B2

公开(公告)日：2004-06-15

申请号：US10355538

申请日：2003-01-30

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

摘要翻译： 本发明包括形成导电互连的方法。 电节点位置被定义为由含硅衬底支撑。 形成与电节点位置接触的硅化物。 硅化物通过将衬底暴露于氢气，TiCl 4和等离子体条件来形成，以使来自TiCl 4的Ti与衬底的硅结合形成TiSix。 在硅化物上形成导电掺杂的硅材料。 导电掺杂的硅材料暴露于至少约800℃的一个或多个温度。硅化物还暴露于至少约800℃的温度

公开(公告)号：US06531352B1

公开(公告)日：2003-03-11

申请号：US09653151

申请日：2000-08-31

申请人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

发明人： Gurtej S. Sandhu ,  Trung Tri Doan ,  Howard E. Rhodes ,  Sujit Sharan ,  Philip J. Ireland ,  Martin Ceredig Roberts

IPC分类号： H01L218238

CPC分类号： H01L21/76877 ,  H01L21/28518

摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

公开(公告)号：US20060218762A1

公开(公告)日：2006-10-05

申请号：US11421701

申请日：2006-06-01

申请人： Gurtej Sandhu ,  Sujit Sharan ,  Neal Rueger ,  Allen Mardian

发明人： Gurtej Sandhu ,  Sujit Sharan ,  Neal Rueger ,  Allen Mardian

IPC分类号： H01L21/00 ,  H01L21/306 ,  C23C16/00

CPC分类号： G01F1/40 ,  G01F1/42 ,  G01P13/0006 ,  G01P13/0013 ,  G01P13/0033 ,  G05D7/0635 ,  Y10T137/0396 ,  Y10T137/7722 ,  Y10T137/775 ,  Y10T137/8242

摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.