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1.发明授权Method and circuit for implementing enhanced SRAM write and read performance ring oscillator 失效实现增强型SRAM写和读性能环形振荡器的方法和电路公开(公告)号：US07684263B2
公开(公告)日：2010-03-23
申请号：US12015806
申请日：2008-01-17
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.
摘要翻译： 一种用于实现增强型静态随机存取存储器（SRAM）读写性能环形振荡器的方法和电路，以及设置有被摄体电路所在的设计结构。 多个SRAM基块在链中连接在一起。 多个SRAM基块中的每一个包括诸如八晶体管（8T）静态随机存取存储器（SRAM）单元的SRAM单元，以及耦合到SRAM单元的局部评估块。 SRAM单元包括独立的左字线输入和右字线输入。 SRAM单元包括一个连接到高电平的读字字线和一个连接低电平的真写补码写位线对。 在本地评估电路中，接收读取位线输入的NAND门的一个输入被连接得很高。 控制信号与反相反馈信号相结合，以启动和停止环形振荡器。
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2.发明申请METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEARCH TIMING FOR CAM COMPARE 有权用于CAM比较的增强比较和搜索时序的方法和寻址小区编码器公开(公告)号：US20060087873A1
公开(公告)日：2006-04-27
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译： 提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。 应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。 然后将编码的真实和补码位信号应用于关键路径动态比较电路。 编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。
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3.发明授权Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare 有权方法和和寻址单元编码器，用于CAM比较的增强比较和搜索时序公开(公告)号：US07035127B1
公开(公告)日：2006-04-25
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译： 提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。 应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。 然后将编码的真实和补码位信号应用于关键路径动态比较电路。 编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。
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4.发明授权Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage 失效实现对多米诺骨牌SRAM的局部评估，具有增强的SRAM单元稳定性，同时最小化区域使用率公开(公告)号：US07724586B2
公开(公告)日：2010-05-25
申请号：US12195151
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。
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5.发明授权Lower power and reduced device split local and continuous bitline for domino read SRAMs 有权降低功耗和减少器件分割本地和连续位线用于多米诺式读取SRAM公开(公告)号：US06901003B2
公开(公告)日：2005-05-31
申请号：US10616847
申请日：2003-07-10
IPC分类号： G11C7/18 , G11C11/419 , G11C11/00
CPC分类号： G11C7/18 , G11C11/419
摘要： A method, an apparatus, and a computer program are provided to reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.
摘要翻译： 提供了一种方法，装置和计算机程序来从SRAM单元读取标记。 在写真线上生成一个低值。 在连续的位线上生成高值。 通过使用耦合到SRAM单元的真实节点的浮动电压来评估SRAM单元的真实节点。 如果浮置电压保持大致恒定，则从SRAM单元读取的值为高。 如果浮置电压耗尽地，则从SRAM单元读取的值为低电平。
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公开(公告)号：US06657886B1
公开(公告)日：2003-12-02
申请号：US10140549
申请日：2002-05-07
IPC分类号： G11C1140
CPC分类号： G11C11/419
摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.
摘要翻译： 提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。 多米诺SRAM包括多个本地小区组。 多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。 连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。 要写入SRAM单元补码节点，只需要驱动连续的补码位线。 与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。
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7.发明授权公开(公告)号：US07835176B2
公开(公告)日：2010-11-16
申请号：US12360230
申请日：2009-01-27
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C7/1045 , G11C8/18 , G11C11/412 , G11C11/413
摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
摘要翻译： 一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。 双模SRAM PSRO包括连接在一起的多个SRAM基块。 多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。 八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。 双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。
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公开(公告)号：US07015600B2
公开(公告)日：2006-03-21
申请号：US10268287
申请日：2002-10-10
摘要： A pulse generator circuit is disclosed including a delay element coupled to a logic circuit. The delay element receives a clock signal CLK and a signal X and produces a signal XN dependent upon the clock signal CLK and the signal X. The logic circuit receives the clock signal CLK and the signal XN and produces a signal ACLK such that ACLK=CLK·XN′. The signal ACLK may include a series of positive pulses. The delay element may be, for example, one of multiple delay elements coupled in series, and signal X may be an output of a preceding one of the delay elements. A semiconductor device is described including the above pulse generator circuit and a self-resetting logic circuit. The self-resetting logic circuit receives the signal ACLK and one or more input signals and performs a logic operation using the one or more input signals during the positive pulses. The semiconductor device may include, for example, a random access memory (RAM) device, and the self-resetting logic circuit may form a part of a decoder circuit of the RAM device.
摘要翻译： 公开了一种脉冲发生器电路，其包括耦合到逻辑电路的延迟元件。 延迟元件接收时钟信号CLK和信号X，并产生取决于时钟信号CLK和信号X的信号XN。逻辑电路接收时钟信号CLK和信号XN，并产生信号ACLK，使得ACLK = CLK .XN'。 信号ACLK可以包括一系列正脉冲。 延迟元件可以是例如串联耦合的多个延迟元件中的一个，并且信号X可以是先前的一个延迟元件的输出。 描述了包括上述脉冲发生器电路和自复位逻辑电路的半导体器件。 自复位逻辑电路接收信号ACLK和一个或多个输入信号，并在正脉冲期间使用一个或多个输入信号执行逻辑运算。 半导体器件可以包括例如随机存取存储器（RAM）器件，并且自复位逻辑电路可以形成RAM器件的解码器电路的一部分。
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9.发明申请公开(公告)号：US20100188888A1
公开(公告)日：2010-07-29
申请号：US12360230
申请日：2009-01-27
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C7/1045 , G11C8/18 , G11C11/412 , G11C11/413
摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
摘要翻译： 一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。 双模SRAM PSRO包括连接在一起的多个SRAM基块。 多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。 八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。 双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。
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10.发明申请Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage 失效实现具有增强的SRAM单元稳定性和增强区域使用的Domino读取SRAM的本地评估公开(公告)号：US20100046278A1
公开(公告)日：2010-02-25
申请号：US12195151
申请日：2008-08-20
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。
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