公开(公告)号：US09543420B2

公开(公告)日：2017-01-10

申请号：US13946613

申请日：2013-07-19

申请人： Wen-Yi Chen ,  Chai Ean Gill

发明人： Wen-Yi Chen ,  Chai Ean Gill

IPC分类号： H01L29/49 ,  H01L29/73 ,  H01L29/66 ,  H01L29/735 ,  H01L27/02 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/73 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/735

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.

摘要翻译： 提供了保护装置结构和相关制造方法。 示例性半导体保护装置包括具有第一导电类型的半导体材料的基极区域，在具有相反导电类型的基极区域内的发射极区域和具有第二导电类型的半导体材料的集电极区域，其中至少一部分 基极区域位于发射极区域和集电极区域之间。 集电极区域的深度大于发射极区域的深度并且小于或等于基极区域的深度，使得发射极区域的横向边界与集电极区域的近侧横向边界之间的距离更大 并且集电极区域不与发射极区域重叠或以其它方式叠加。

公开(公告)号：US09054155B2

公开(公告)日：2015-06-09

申请号：US13789340

申请日：2013-03-07

申请人： Chai Ean Gill ,  Wen-Yi Chen

发明人： Chai Ean Gill ,  Wen-Yi Chen

IPC分类号： H01L27/02 ,  H01L21/76 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L27/0251 ,  H01L27/1203

摘要： Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.

摘要翻译： 提供了电子器件封装的芯片结构和相关的制造方法。 示例性管芯结构包括具有包括形成在其上的半导体器件的半导体材料的第一层，半导体材料的手柄层以及处理层和第一层之间的介电材料掩埋层的衬底。 模具结构还包括在第一半导体材料层中的多个分流区域，其中每个分流区域包括电连接到半导体材料的手柄层的第一层中的掺杂区域和掺杂区域下面的体区域 其与半导体器件下面的第一层的至少一部分相邻。

公开(公告)号：US09112351B2

公开(公告)日：2015-08-18

申请号：US13759241

申请日：2013-02-05

申请人： Wen-Yi Chen ,  Chai Ean Gill

发明人： Wen-Yi Chen ,  Chai Ean Gill

IPC分类号： H02H9/04 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

摘要翻译： 提供集成电路。 集成电路可以包括但不限于第一节点，被配置为耦合到地的第二节点，输出驱动器和电耦合到第一节点，第二节点和输出驱动器的静电放电电路 。 静电放电电路可以包括但不限于被配置为检测第一节点处的静电放电事件的高通滤波器，电耦合到高通滤波器和输出驱动器的驱动级电路，驱动级电路配置 当所述高通滤波器检测到所述静电放电事件时，接收来自所述高通滤波器的信号，并且还被配置为响应于来自所述高通滤波器的信号将所述输出驱动器的输入分流到所述第二节点，并且 降压电路电耦合到驱动级电路并且被配置为偏置驱动级电路。

公开(公告)号：US20140252552A1

公开(公告)日：2014-09-11

申请号：US13789340

申请日：2013-03-07

申请人： Chai Ean Gill ,  Wen-Yi Chen

发明人： Chai Ean Gill ,  Wen-Yi Chen

IPC分类号： H01L27/02 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L27/0251 ,  H01L27/1203

摘要： Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.

摘要翻译： 提供了电子器件封装的芯片结构和相关的制造方法。 示例性管芯结构包括具有包括形成在其上的半导体器件的半导体材料的第一层，半导体材料的手柄层以及处理层和第一层之间的介电材料掩埋层的衬底。 模具结构还包括在第一半导体材料层中的多个分流区域，其中每个分流区域包括电连接到半导体材料的手柄层的第一层中的掺杂区域和掺杂区域下面的体区域 其与半导体器件下面的第一层的至少一部分相邻。

公开(公告)号：US09502890B2

公开(公告)日：2016-11-22

申请号：US13900226

申请日：2013-05-22

申请人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

IPC分类号： H01L29/66 ,  H01L27/02 ,  H02H9/04 ,  H01L29/732

CPC分类号： H02H9/044 ,  H01L27/0259 ,  H01L29/7322 ,  H02H9/046

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.

摘要翻译： 提供了保护装置结构和相关制造方法。 一种示例性的半导体保护装置包括具有第一导电类型的半导体材料的第一基极区域，具有第一导电类型的第二基极区域和具有小于第一基极区域的掺杂剂浓度的第二基极区域，半导体的第三基极区域 具有第一导电类型和大于第二基极区的掺杂剂浓度的材料，具有与第一基极区内的第一导电类型相反的第二导电类型的半导体材料的发射极区域和具有第一导电类型的半导体材料的集电极区域， 第二导电类型。 第二基极区域的至少一部分位于第三基极区域和第一基极区域之间，并且第一基极区域的至少一部分位于发射极区域和集电极区域之间。

公开(公告)号：US09129806B2

公开(公告)日：2015-09-08

申请号：US13900256

申请日：2013-05-22

申请人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Wen-Yi Chen ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/66 ,  H01L27/02

CPC分类号： H01L27/0259

摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.

摘要翻译： 提供了保护装置结构和相关制造方法。 示例性的半导体保护装置包括具有第一导电类型的基极阱区域，在基极阱区域内的发射极区域具有与第一导电类型相反的第二导电类型，具有第二导电类型的集电极区域，具有第二导电类型的第一浮动区域， 在发射极区域和集电极区域之间的基极阱区域内的第二导电类型，以及在第一浮动区域和集电极区域之间的基极阱区域内具有第一导电类型的第二浮动区域。 基极区域内的浮动区域电连接以减小电流增益并改善保持电压。

公开(公告)号：US20140218829A1

公开(公告)日：2014-08-07

申请号：US13759241

申请日：2013-02-05

申请人： Wen-Yi Chen ,  Chai Ean Gill

发明人： Wen-Yi Chen ,  Chai Ean Gill

IPC分类号： H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0285

摘要： An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

摘要翻译： 提供集成电路。 集成电路可以包括但不限于第一节点，被配置为耦合到地的第二节点，输出驱动器和电耦合到第一节点，第二节点和输出驱动器的静电放电电路 。 静电放电电路可以包括但不限于被配置为检测第一节点处的静电放电事件的高通滤波器，电耦合到高通滤波器和输出驱动器的驱动级电路，驱动级电路配置 当所述高通滤波器检测到所述静电放电事件时，接收来自所述高通滤波器的信号，并且还被配置为响应于来自所述高通滤波器的信号将所述输出驱动器的输入分流到所述第二节点，并且 降压电路电耦合到驱动级电路并且被配置为偏置驱动级电路。

公开(公告)号：US09786652B2

公开(公告)日：2017-10-10

申请号：US14854366

申请日：2015-09-15

申请人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

发明人： Rouying Zhan ,  Chai Ean Gill ,  Changsoo Hong ,  Michael H. Kaneshiro

IPC分类号： H01L29/74 ,  H01L29/747 ,  H01L29/00 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L27/02 ,  H01L29/66 ,  H01L23/60 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/082 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/73 ,  H01L29/7317 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

公开(公告)号：US20130279051A1

公开(公告)日：2013-10-24

申请号：US13451312

申请日：2012-04-19

申请人： Chai Ean Gill ,  Rouying Zhan

发明人： Chai Ean Gill ,  Rouying Zhan

IPC分类号： H02H9/04

CPC分类号： H01L27/0259 ,  H02H9/041

摘要： An area-efficient, high voltage, dual polarity ESD protection device (200) is provided for protecting multiple pins (30, 40) against ESD events by using a plurality of stacked NPN devices (38, 48, 39) which have separately controllable breakdown voltages and which share one or common NPN devices (39), thereby reducing the footprint of the high voltage ESD protection circuits without reducing robustness and functionality.

摘要翻译： 提供了一种区域高效，高电压，双极性ESD保护装置（200），用于通过使用多个堆叠的NPN装置（38,48,39）来保护多个针脚（30,40）免受ESD事件的影响，这些NPN装置具有分别可控的击穿 电压并且共享一个或公共NPN器件（39），从而减少高压ESD保护电路的覆盖，而不降低鲁棒性和功能性。

公开(公告)号：US08279566B2

公开(公告)日：2012-10-02

申请号：US12112209

申请日：2008-04-30

申请人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

发明人： James D. Whitfield ,  Chai Ean Gill ,  Abhijat Goyal ,  Rouying Zhan

IPC分类号： H02H9/00

CPC分类号： H01L27/0248

摘要： An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35′) with gates (38, 38′) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT (25) during normal operation is much reduced.

摘要翻译： 被保护半导体SC器件的输入输出（I / O）（22）和公共（GND）（23）端子耦合的静电放电（ESD）钳位（41,41,61,71,81,91） IC（24）包括耦合在GND（23）和I / O（22）之间的源极 - 漏极（26,27）的ESD晶体管（ESDT）（25），耦合在栅极 28）和源极（26）以及耦合在ESDT体（29）和源极（26）之间的第二电阻器（30）。 并联电阻器（30,32）是与一个或多个偏置电源Vb，Vb'耦合的门（38,38'）的控制晶体管（35,35'）。 设备或IC（24）的主电源轨（Vdd）是Vb，Vb'的方便源。 当Vdd在装运，处理，设备组装等时关闭时，ESD触发电压Vt1为低，从而在ESD风险高时提供最大的ESD保护。 当Vdd通电时，Vt1上升到足够大的值，以避免与正常电路操作的干扰，但仍然保护ESD事件。 在正常运行期间通过ESDT（25）的寄生泄漏大大减少。