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    SEMICONDUCTOR DEVICE USING POWER GATING
    1.
    发明申请
    SEMICONDUCTOR DEVICE USING POWER GATING 有权
    使用功率增益的半导体器件

    公开(公告)号：US20100097097A1

    公开(公告)日：2010-04-22

    申请号：US12288249

    申请日：2008-10-17

    申请人： Suhwan Kim ,  Chang-jun Choi

    发明人： Suhwan Kim ,  Chang-jun Choi

    IPC分类号： H03K17/16 ,  G05F3/02

    CPC分类号： H03K19/0016 ,  H03K19/00361

    摘要： A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

    摘要翻译： 使用电源门控的半导体器件包括电路单元和电流阻挡单元。 电路单元连接在第一电压节点和虚拟电压节点之间。 电流阻断单元连接在虚拟电压节点和第二电压节点之间，并且可以在待机模式下阻断电路单元的漏电流。 此外，当待机模式切换到活动模式时，当前阻塞单元响应于逻辑状态被随机转移的多个随机信号来控制是否连接虚拟电压节点和第二电压节点。 半导体器件可以最小化地面反弹噪声，并可以稳定地将电压施加到以数据保持模式存储数据的电路。

    Semiconductor device using power gating
    4.
    发明授权
    Semiconductor device using power gating 有权
    半导体器件采用电源门控

    公开(公告)号：US07705627B1

    公开(公告)日：2010-04-27

    申请号：US12288249

    申请日：2008-10-17

    申请人： Suhwan Kim ,  Chang-jun Choi

    发明人： Suhwan Kim ,  Chang-jun Choi

    IPC分类号： H03K19/003

    CPC分类号： H03K19/0016 ,  H03K19/00361

    摘要： A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode.

    摘要翻译： 使用电源门控的半导体器件包括电路单元和电流阻挡单元。 电路单元连接在第一电压节点和虚拟电压节点之间。 电流阻断单元连接在虚拟电压节点和第二电压节点之间，并且可以在待机模式下阻断电路单元的漏电流。 此外，当待机模式切换到活动模式时，当前阻塞单元响应于逻辑状态被随机转移的多个随机信号来控制是否连接虚拟电压节点和第二电压节点。 半导体器件可以最小化地面反弹噪声，并可以稳定地将电压施加到以数据保持模式存储数据的电路。

    Power control circuit for semiconductor IC
    5.
    发明授权
    Power control circuit for semiconductor IC 有权
    半导体IC功率控制电路

    公开(公告)号：US07643368B2

    公开(公告)日：2010-01-05

    申请号：US11969968

    申请日：2008-01-07

    申请人： Chang-Jun Choi ,  Suhwan Kim

    发明人： Chang-Jun Choi ,  Suhwan Kim

    IPC分类号： G11C5/14

    CPC分类号： G11C5/145

    摘要： A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode.

    摘要翻译： 公开了向在半导体集成电路内提供逻辑块的输出端子提供电力的功率控制电路和相关方法。 功率控制电路包括电源门控电路，其在正常操作模式期间向输出端提供主电源电压，并且在数据保持模式期间向输出端提供保持电压，其特征在于不存在来自逻辑块的主电源电压 ，其中所述保持电压最小程度足以在所述数据保持模式期间保留存储在所述逻辑块中的数据。

    Door for oven and an oven
    7.
    发明授权
    Door for oven and an oven 有权
    炉门和烤箱

    公开(公告)号：US09151505B2

    公开(公告)日：2015-10-06

    申请号：US13553732

    申请日：2012-07-19

    申请人： Suhwan Kim ,  Yungeon Baek ,  Byoungwoo Choi

    发明人： Suhwan Kim ,  Yungeon Baek ,  Byoungwoo Choi

    IPC分类号： F24C15/02

    CPC分类号： F24C15/02

    摘要： A door for an oven and the oven are provided. The door includes a door frame and a door panel where the door panel is coupled to the door frame. The door panel includes a front panel, a top panel bent from an upper end of the front panel to form a topside of the door, the top panel having a first bent portion spaced from the front panel to contact a top side of the door frame, and a pair of side panels, each side panel being bent from a lateral side of the front panel to form lateral sides of the door, and each side panel having a second bent portion spaced from the front panel to contact sides of the door frame.

    摘要翻译： 提供烤箱和烤箱门。 门包括门框和门面板，门面板联接到门框。 门板包括前板，顶板从前板的上端弯曲以形成门顶部，顶板具有与前板间隔开的第一弯曲部分，以接触门框的顶侧 和一对侧板，每个侧板从前面板的侧面弯曲形成门的侧面，并且每个侧板具有与前板间隔开的第二弯曲部分，以与门框的侧面接触 。

    A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT
    9.
    发明申请
    A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT 审中-公开
    一种用于控制集成电路中的功耗的方法和装置

    公开(公告)号：US20060064606A1

    公开(公告)日：2006-03-23

    申请号：US10711485

    申请日：2004-09-21

    申请人： Suhwan Kim ,  Stephen Kosonocky ,  Peter Sandon

    发明人： Suhwan Kim ,  Stephen Kosonocky ,  Peter Sandon

    IPC分类号： G06F1/26

    CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152

    摘要： A method and apparatus for controlling power consumption by devices in an integrated circuit. The apparatus includes a complementary device for a corresponding device for which power consumption is desired to be reduced. The complementary device supports all or some of the tasks of the corresponding device. The complementary device receives tasks that can be executed by either itself or the corresponding device and based upon the power management scheme will either execute the task itself or allow the corresponding device.

    摘要翻译： 一种用于控制集成电路中的器件的功耗的方法和装置。 该装置包括用于相应设备的补充设备，期望降低功耗。 互补设备支持相应设备的全部或部分任务。 互补设备接收可以由其自身或相应设备执行的任务，并且基于功率管理方案将执行任务本身或允许相应的设备。

    Non-abrupt switching of sleep transistor of power gate structure
    10.
    发明授权
    Non-abrupt switching of sleep transistor of power gate structure 有权
    功率门结构睡眠晶体管的非突然切换

    公开(公告)号：US06876252B2

    公开(公告)日：2005-04-05

    申请号：US10609360

    申请日：2003-06-28

    申请人： Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

    发明人： Suhwan Kim ,  Daniel R. Knebel ,  Stephen V. Kosonocky

    IPC分类号： H03K17/16 ,  H03K17/72

    CPC分类号： H03K17/163 ,  H03K17/164

    摘要： A semiconductor integrated circuit including a non-abrupt switching mechanism for a sleep transistor of a power gate structure to reduce ground bounce is provided. The semiconductor integrated circuit comprises a supply voltage line; a ground voltage line; a virtual ground voltage line; a logic circuit coupled to the supply voltage line and the virtual ground voltage line; at least one sleep transistor for controlling current flow to the logic circuit, the sleep transistor being coupled to the virtual ground voltage line and the ground voltage line; and a non-abrupt switching circuit for sequentially controlling the sleep transistor. The switching mechanism reduces the magnitude of voltage glitches on the power and ground rails as well as the minimum time required to stabilize power and ground.

    摘要翻译： 提供一种包括用于减少地面反弹的功率门结构的休眠晶体管的非突变切换机构的半导体集成电路。 半导体集成电路包括电源电压线; 地电压线; 虚拟地电压线; 耦合到电源电压线和虚拟接地电压线的逻辑电路; 至少一个睡眠晶体管，用于控制到逻辑电路的电流，睡眠晶体管耦合到虚拟接地电压线和地电压线; 以及用于依次控制睡眠晶体管的非突变切换电路。 开关机构可以减少电源和接地导轨上的电压毛刺的大小以及稳定电源和接地所需的最短时间。