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1.发明申请STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME 有权具有绝缘层和二次层的堆叠CMOS芯片及其形成方法公开(公告)号：US20130120951A1
公开(公告)日：2013-05-16
申请号：US13356717
申请日：2012-01-24
申请人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
CPC分类号： H01L27/0688 , H01L2224/18
摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。
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公开(公告)号：US20130113076A1
公开(公告)日：2013-05-09
申请号：US13293075
申请日：2011-11-09
申请人： Changhan YUN , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan YUN , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
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公开(公告)号：US09008602B2
公开(公告)日：2015-04-14
申请号：US13464092
申请日：2012-05-04
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
CPC分类号： H04B7/0805 , H04B1/005 , H04B1/16 , H04B1/18 , H04B7/0825
摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
摘要翻译： 分集接收机交换机包括被配置为与收发机通信的至少一个第二级交换机。 分集接收机交换机还可以包括耦合在分集接收机天线和第二级交换机之间的至少一个第一级交换机。 第一级开关可以被配置为处理与第二级开关不同的功率量。 分集接收器开关可以包括被配置为与收发器通信的一组第二级交换机。 第一级开关可以被配置为处理比第二级开关组中的每个开关更多的功率。 或者，分集接收器开关包括耦合在分集接收器天线和第二级开关之间的一组第一级开关。 第二级开关可以被配置为处理比每个第一级开关更多的功率。
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公开(公告)号：US08907450B2
公开(公告)日：2014-12-09
申请号：US13293075
申请日：2011-11-09
申请人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
摘要翻译： 提供了用于高Q装置的金属半导体晶片接合的方法和装置。 示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。 在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。 重掺杂的非本征半导体层接触电介质层。 电介质和非本征半导体层夹在第一和第二板之间。 在第一板和电介质层之间形成金属间层。 金属间化合物层被热压接合到第一板和电介质层。 电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。
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公开(公告)号：US20130295866A1
公开(公告)日：2013-11-07
申请号：US13464092
申请日：2012-05-04
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Mario F. Velez , Jonghae Kim
IPC分类号： H04B1/16
CPC分类号： H04B7/0805 , H04B1/005 , H04B1/16 , H04B1/18 , H04B7/0825
摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.
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公开(公告)号：US20130207745A1
公开(公告)日：2013-08-15
申请号：US13419876
申请日：2012-03-14
申请人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
发明人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
CPC分类号： H03H7/0115 , H01F17/0013 , H01F17/0033 , H01F2017/0026 , H01F2017/004 , H03H7/09 , H03H7/1708 , H03H7/1766 , H03H7/1775 , H03H7/1783 , H03H2001/0085 , Y10T29/4913
摘要： Three-dimensional (3D) Radio Frequency (RF) inductor-capacitor (LC) band pass filters having through-glass-vias (TGVs). One such L-C filter circuit includes a glass substrate, a first portion of a first inductor formed on a first surface of the glass substrate, a second portion of the first inductor formed on a second surface of the glass substrate, and a first set of TGVs configured to connect the first and second portions of the first inductor. Additionally the L-C filter circuit can include a second inductor similar to the first inductor, and a metal-insulator-metal (MIM) capacitor formed between the first and second inductor, such that the first and second inductor are coupled through the MIM capacitor.
摘要翻译： 具有透玻璃通孔（TGV）的三维（3D）射频（RF）电感 - 电容（LC）带通滤波器。 一个这样的LC滤波器电路包括玻璃基板，形成在玻璃基板的第一表面上的第一电感器的第一部分，形成在玻璃基板的第二表面上的第一电感器的第二部分和第一组TGV 被配置为连接第一电感器的第一和第二部分。 此外，L-C滤波器电路可以包括类似于第一电感器的第二电感器和形成在第一和第二电感器之间的金属 - 绝缘体 - 金属（MIM）电容器，使得第一和第二电感器通过MIM电容器耦合。
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7.发明授权Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same 有权具有绝缘层和二次层的叠层CMOS芯片组及其形成方法公开(公告)号：US09496255B2
公开(公告)日：2016-11-15
申请号：US13356717
申请日：2012-01-24
申请人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Sang-June Park , Chi Shun Lo , Mario F. Velez , Jonghae Kim
CPC分类号： H01L27/0688 , H01L2224/18
摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.
摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。
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公开(公告)号：US5454270A
公开(公告)日：1995-10-03
申请号：US254849
申请日：1994-06-06
CPC分类号： G01L19/0084 , G01L19/0038
摘要： A differential pressure sensor (10) has a sensor die (16) attached to a stress isolation package base (12) with a bonding glass (27) having a similar coefficient of thermal expansion. The bonding glass, and alternately an aluminum layer, provides a hermetic seal between the stress isolation base and sensor die. Pressure is applied to the sensor die port (24). A plastic housing (14) is attached to the stress isolation base with an adhesive (29). A port (23) in the plastic housing is filled with a silicone gel (22). A second pressure source is transferred by way of the silicone gel to the sensor die. Any hostile chemical entering the via contacts the first surface of the sensor die to assert pressure against a transducer circuit (25) to generate the electrical signals representative of the applied pressure but are isolated from the sensitive interconnects by the hermetic seal.
摘要翻译： 差压传感器（10）具有通过具有相似热膨胀系数的粘合玻璃（27）附接到应力隔离封装基座（12）的传感器管芯（16）。 粘合玻璃，或者铝层，在应力隔离基底和传感器模具之间提供气密密封。 压力被施加到传感器模具端口（24）。 用粘合剂（29）将塑料外壳（14）附接到应力隔离基座上。 塑料外壳中的端口（23）填充有硅胶（22）。 第二压力源通过硅胶转移到传感器模头。 进入通孔的任何不利的化学物质接触传感器管芯的第一表面，以便相对于换能器电路（25）施加压力，以产生代表所施加的压力的电信号，但是通过气密密封与敏感互连件隔离。
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