公开(公告)号：US20130120951A1

公开(公告)日：2013-05-16

申请号：US13356717

申请日：2012-01-24

申请人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H05K1/03 ,  H01L21/60 ,  H05K7/06 ,  H01L21/58

CPC分类号： H01L27/0688 ,  H01L2224/18

摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.

摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。

公开(公告)号：US09496255B2

公开(公告)日：2016-11-15

申请号：US13356717

申请日：2012-01-24

申请人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H01L21/00 ,  H01L27/06

CPC分类号： H01L27/0688 ,  H01L2224/18

摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.

摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。

公开(公告)号：US09008602B2

公开(公告)日：2015-04-14

申请号：US13464092

申请日：2012-05-04

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H04B1/06 ,  H04B1/44 ,  H03C7/02 ,  H01Q11/12 ,  H04M1/00 ,  H04B1/16 ,  H04B1/00 ,  H04B7/08

CPC分类号： H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

摘要翻译： 分集接收机交换机包括被配置为与收发机通信的至少一个第二级交换机。 分集接收机交换机还可以包括耦合在分集接收机天线和第二级交换机之间的至少一个第一级交换机。 第一级开关可以被配置为处理与第二级开关不同的功率量。 分集接收器开关可以包括被配置为与收发器通信的一组第二级交换机。 第一级开关可以被配置为处理比第二级开关组中的每个开关更多的功率。 或者，分集接收器开关包括耦合在分集接收器天线和第二级开关之间的一组第一级开关。 第二级开关可以被配置为处理比每个第一级开关更多的功率。

公开(公告)号：US08907450B2

公开(公告)日：2014-12-09

申请号：US13293075

申请日：2011-11-09

申请人： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

发明人： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

IPC分类号： H01L29/92 ,  H01L21/02 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC分类号： H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

摘要翻译： 提供了用于高Q装置的金属半导体晶片接合的方法和装置。 示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。 在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。 重掺杂的非本征半导体层接触电介质层。 电介质和非本征半导体层夹在第一和第二板之间。 在第一板和电介质层之间形成金属间层。 金属间化合物层被热压接合到第一板和电介质层。 电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

公开(公告)号：US20130295866A1

公开(公告)日：2013-11-07

申请号：US13464092

申请日：2012-05-04

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H04B1/16

CPC分类号： H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

摘要： A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

公开(公告)号：US20130113076A1

公开(公告)日：2013-05-09

申请号：US13293075

申请日：2011-11-09

申请人： Changhan YUN ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

发明人： Changhan YUN ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

IPC分类号： H01L21/02 ,  H01L29/92

CPC分类号： H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

公开(公告)号：US20130207745A1

公开(公告)日：2013-08-15

申请号：US13419876

申请日：2012-03-14

申请人： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

发明人： Changhan Yun ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

IPC分类号： H03H7/01 ,  H05K3/30

CPC分类号： H03H7/0115 ,  H01F17/0013 ,  H01F17/0033 ,  H01F2017/0026 ,  H01F2017/004 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/1783 ,  H03H2001/0085 ,  Y10T29/4913

摘要： Three-dimensional (3D) Radio Frequency (RF) inductor-capacitor (LC) band pass filters having through-glass-vias (TGVs). One such L-C filter circuit includes a glass substrate, a first portion of a first inductor formed on a first surface of the glass substrate, a second portion of the first inductor formed on a second surface of the glass substrate, and a first set of TGVs configured to connect the first and second portions of the first inductor. Additionally the L-C filter circuit can include a second inductor similar to the first inductor, and a metal-insulator-metal (MIM) capacitor formed between the first and second inductor, such that the first and second inductor are coupled through the MIM capacitor.

摘要翻译： 具有透玻璃通孔（TGV）的三维（3D）射频（RF）电感 - 电容（LC）带通滤波器。 一个这样的LC滤波器电路包括玻璃基板，形成在玻璃基板的第一表面上的第一电感器的第一部分，形成在玻璃基板的第二表面上的第一电感器的第二部分和第一组TGV 被配置为连接第一电感器的第一和第二部分。 此外，L-C滤波器电路可以包括类似于第一电感器的第二电感器和形成在第一和第二电感器之间的金属 - 绝缘体 - 金属（MIM）电容器，使得第一和第二电感器通过MIM电容器耦合。

公开(公告)号：US09083300B2

公开(公告)日：2015-07-14

申请号：US13094707

申请日：2011-04-26

申请人： Chi Shun Lo ,  Jonghae Kim ,  Sang-June Park ,  Sanghoon Joo ,  Chengjie Zuo ,  Changhan Yun

发明人： Chi Shun Lo ,  Jonghae Kim ,  Sang-June Park ,  Sanghoon Joo ,  Chengjie Zuo ,  Changhan Yun

IPC分类号： H03H9/70 ,  H03H9/00 ,  H01P1/213 ,  H03H9/02 ,  H03H9/24 ,  H03H9/56 ,  G09G3/34 ,  H03H3/02

CPC分类号： H03H9/0095 ,  G09G3/3493 ,  G09G2310/0267 ,  G09G2310/027 ,  H01P1/2135 ,  H03H9/0014 ,  H03H9/02228 ,  H03H9/2431 ,  H03H9/2436 ,  H03H9/2463 ,  H03H9/564 ,  H03H2003/027 ,  H03H2009/02496 ,  H03H2009/02527 ,  H03H2009/241

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a contour mode resonator device includes a first conductive layer with a plurality of first layer electrodes including a first electrode at which a first input signal can be provided and a second electrode at which a first output signal can be provided. A second conductive layer includes a plurality of second layer electrodes including a first electrode proximate the first electrode of the first conductive layer and a second electrode proximate the second electrode of the first conductive layer. A second signal can be provided at the first electrode or the second electrode of the second conductive layer to cooperate with the first input signal or the first output signal to define a differential signal. A piezoelectric layer is disposed between the first conductive layer and the second conductive layer. The piezoelectric layer includes a piezoelectric material. The piezoelectric layer is substantially oriented in a plane and capable of movement in the plane responsive to an electric field between the first electrodes or the second electrodes.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 一方面，轮廓模式谐振器装置包括具有多个第一层电极的第一导电层，所述第一导电层包括能够提供第一输入信号的第一电极和可以提供第一输出信号的第二电极。 第二导电层包括多个第二层电极，其包括靠近第一导电层的第一电极的第一电极和靠近第一导电层的第二电极的第二电极。 可以在第二导电层的第一电极或第二电极处提供第二信号，以与第一输入信号或第一输出信号配合以限定差分信号。 压电层设置在第一导电层和第二导电层之间。 压电层包括压电材料。 压电层基本上定向在平面中并且能够响应于第一电极或第二电极之间的电场在平面中移动。

公开(公告)号：US20120050236A1

公开(公告)日：2012-03-01

申请号：US13094707

申请日：2011-04-26

申请人： Chi Shun Lo ,  Jonghae Kim ,  Sang-June Park ,  Sanghoon Joo ,  Chengjie Zuo ,  Changhan Yun

发明人： Chi Shun Lo ,  Jonghae Kim ,  Sang-June Park ,  Sanghoon Joo ,  Chengjie Zuo ,  Changhan Yun

IPC分类号： H01P7/00 ,  H04B1/04 ,  H04B1/06 ,  H01P5/12 ,  G09G5/00

CPC分类号： H03H9/0095 ,  G09G3/3493 ,  G09G2310/0267 ,  G09G2310/027 ,  H01P1/2135 ,  H03H9/0014 ,  H03H9/02228 ,  H03H9/2431 ,  H03H9/2436 ,  H03H9/2463 ,  H03H9/564 ,  H03H2003/027 ,  H03H2009/02496 ,  H03H2009/02527 ,  H03H2009/241

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a contour mode resonator device includes a first conductive layer with a plurality of first layer electrodes including a first electrode at which a first input signal can be provided and a second electrode at which a first output signal can be provided. A second conductive layer includes a plurality of second layer electrodes including a first electrode proximate the first electrode of the first conductive layer and a second electrode proximate the second electrode of the first conductive layer. A second signal can be provided at the first electrode or the second electrode of the second conductive layer to cooperate with the first input signal or the first output signal to define a differential signal. A piezoelectric layer is disposed between the first conductive layer and the second conductive layer. The piezoelectric layer includes a piezoelectric material. The piezoelectric layer is substantially oriented in a plane and capable of movement in the plane responsive to an electric field between the first electrodes or the second electrodes.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 一方面，轮廓模式谐振器装置包括具有多个第一层电极的第一导电层，所述第一导电层包括能够提供第一输入信号的第一电极和可以提供第一输出信号的第二电极。 第二导电层包括多个第二层电极，其包括靠近第一导电层的第一电极的第一电极和靠近第一导电层的第二电极的第二电极。 可以在第二导电层的第一电极或第二电极处提供第二信号，以与第一输入信号或第一输出信号配合以限定差分信号。 压电层设置在第一导电层和第二导电层之间。 压电层包括压电材料。 压电层基本上定向在平面中并且能够响应于第一电极或第二电极之间的电场在平面中移动。

公开(公告)号：US20130222060A1

公开(公告)日：2013-08-29

申请号：US13406431

申请日：2012-02-27

申请人： Chi Shun Lo ,  Jonghae Kim ,  Wesley Nathaniel Allen ,  Chengjie Zuo ,  Changhan Yun ,  Thomas Andrew Myers ,  Prasad Srinivasa Siva Gudem ,  Matthew Michael Nowak

发明人： Chi Shun Lo ,  Jonghae Kim ,  Wesley Nathaniel Allen ,  Chengjie Zuo ,  Changhan Yun ,  Thomas Andrew Myers ,  Prasad Srinivasa Siva Gudem ,  Matthew Michael Nowak

IPC分类号： H03H7/38 ,  H03F1/00

CPC分类号： H03H7/38 ,  H03H7/09

摘要： An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit.

摘要翻译： 公开了一种阻抗匹配电路。 阻抗匹配电路包括两个或更多个相互耦合的电感器。 阻抗匹配电路的总自感小于包括不相互耦合的电感器的对应阻抗匹配电路。 两个或更多个相互耦合的电感器可以具有与相应的阻抗匹配电路中的电流比匹配的已知电流比。