公开(公告)号：US5036408A

公开(公告)日：1991-07-30

申请号：US193090

申请日：1988-05-12

Applicant: Michael D. Leis ,  Bruce Leshay ,  Michael Muchnik ,  Satish Rege ,  Charles M. Riggle ,  Lih-Jyh Weng

Inventor： Michael D. Leis ,  Bruce Leshay ,  Michael Muchnik ,  Satish Rege ,  Charles M. Riggle ,  Lih-Jyh Weng

IPC: G11B20/10 ,  G11B5/596 ,  G11B20/12 ,  G11B20/14 ,  G11B27/30

CPC classification number: G11B27/3027 ,  G11B20/1217 ,  G11B5/59633 ,  G11B2020/1282 ,  G11B2220/20

Abstract: A disk drive system provides all required synchronization, positioning, validation, and data functions within each disk sector. All of these functions are provided within two zones, a header section and a data section. The header section includes a preamble, a synchronization character and an address field, as well as servo information for track following. The data section of each sector includes a data preamble, a data synchronization character, a bad sector bit map, the data and data redundancy information. The header section of at least one sector in a track includes a short DC-erase field, a transitionless segment which is used in synchronization. To synchronize a read/write head to the disk, the system first detects the DC-erase field. The system next searches for the header premable and synchronization character. If it finds them within predetermined times, it then looks for a valid sector address to complete the synchronization. If the system does not detect the preamble and synchronization character within the predetermined times, it looks for another DC-erase field and continues the synchronization process. After the preamble and synchronization character are found, the desired sector is located by reading the addresses of the succeeding sectors.

公开(公告)号：US4968985A

公开(公告)日：1990-11-06

申请号：US202882

申请日：1988-06-06

Applicant: Charles M. Riggle ,  Lih-Jyh Weng

Inventor： Charles M. Riggle ,  Lih-Jyh Weng

IPC: G06F3/05 ,  G11B20/10 ,  G11B20/14 ,  G11B20/18

CPC classification number: G11B20/10212 ,  G11B20/10037 ,  G11B20/1426 ,  G11B20/18

Abstract: A data demodulator assigns a binary value to the signal recorded in a transition cell based on the amplitude of the signal in the transition cell, the amplitudes of the signal in adjacent transition cells and system experience in categorizing how recording non-linearities and system noise effect the signals. The demodulator samples a selected number of times the recorded signal in the transition cell for which a binary value is to be determined and the recorded signal in a selected number of transition cells adjacent to that cell. It then converts the amplitude of each of the signal samples to a digital symbol. Next, it concatenates portions of the digital symbols to form an interpretation word. It uses this word to enter a stored lookup table which contains binary values, and assigns to the transition cell signal the binary value associated with the word. The table associates a value with a particular word or group of words based on system experience and the demodulation of known signals into interpretation words. The binary values assigned to a number of cells may be combined to form a code word which may be decoded and corrected using soft decoding techniques.

公开(公告)号：US4413339A

公开(公告)日：1983-11-01

申请号：US277060

申请日：1981-06-24

Applicant: Charles M. Riggle ,  Lih-Jyh Weng ,  Norman A. Field

Inventor： Charles M. Riggle ,  Lih-Jyh Weng ,  Norman A. Field

IPC: H03M13/15 ,  G06F11/12

CPC classification number: H03M13/151

Abstract: An error detecting and correcting system implementing the Reed-Solomon (1023, 1006) code having code words whose symbols are elements in the Galois field GF(2.sup.10) generated by either the primitive polynomial x.sup.10 +x.sup.3 +1 or x.sup.10 +x.sup.7 +1. An original data word is encoded to produce a code word w(x) including a first set of checksum symbols appended thereto. Upon retrieval, the data symbols of the receive code word y(x) are encoded by the same encoder that encodes the original data word to produce a second set of checksum symbols. Both sets of checksum symbols are modulo-two summed to produce a residue R(x) from which error syndromes S.sub.i can be computed and thus enable rapid correction of errors in the received code word y(x). The system also monitors the number of non-zero symbols in the residue R(x) in order to avoid unnecessary computation of error syndromes S.sub.i and other decoding routines, such as when the received code word y(x) is otherwise uncorrectable or when the error exists only in the received checksum symbols, rather than in the data symbols. The distance between code words being (2T+ 2), the error correction routine is bypassed when the number of non-zero symbols in R(x) is less than or equal to T, which indicates that errors only reside in the checksum symbols. When the number of non-zero symbols equals (T+1), the error is uncorrectable. For determining whether a single error exists so that correction can quickly be made, the system also tests whether S.sub.i+1 /S.sub.i is constant for all error syndromes S.sub.i.

Abstract translation: 实现具有代码字的Reed-Solomon（1023,1006）代码的错误检测和校正系统，其码元是由原始多项式x10 + x3 + 1或x10 + x7 + 1产生的伽罗瓦域GF（210）中的元素。 原始数据字被编码以产生包括附加到其上的第一组校验和符号的码字w（x）。 在检索时，接收码字y（x）的数据符号由编码原始数据字的相同编码器编码，以产生第二组校验和符号。 两组校验和符号被模二相加以产生残差R（x），从中可以计算出错误综合征Si，从而能够快速校正接收到的代码字y（x）中的错误。 该系统还监视残差R（x）中的非零符号的数目，以避免误差综合征Si和其他解码程序的不必要的计算，例如当接收到的代码字y（x）不可校正时或当 错误仅存在于接收到的校验和符号中，而不是数据符号中。 当R（x）中的非零符号数小于或等于T时，代码字之间的距离为（2T + 2），纠错程序被旁路，这表示错误仅驻留在校验和符号中。 当非零符号的数量等于（T + 1）时，该错误是不可校正的。 为了确定是否存在单一误差以便能够快速进行校正，系统还测试Si + 1 / Si对于所有误差综合征Si是否恒定。

公开(公告)号：US06581180B1

公开(公告)日：2003-06-17

申请号：US09527736

申请日：2000-03-17

Applicant: Lih-Jyh Weng

Inventor： Lih-Jyh Weng

IPC: H03M1300

CPC classification number: H03M13/1545 ,  H03M13/158

Abstract: A system for performing a Chien search simultaneously tests multiple elements of GF(2P) as possible roots of a degree-t error locator polynomial &sgr;(x) using a plurality of simplified multipliers that each simultaneously produce the corresponding terms of &sgr;(x). In one embodiment of the system, t−1 simplified multipliers over GF(2P) are used to simultaneously test as possible roots &agr;2, (&agr;2)2, (&agr;2)3 . . . (&agr;2)j. Each multiplier includes a plurality of adders that are set up in accordance with precomputed terms that are based on combinations of the weight-one elements of GF(2P). A summing circuit adds together the associated terms produced by the multipliers and produces j sums, which are then evaluated to test the j individual elements as possible roots. The coefficients of &sgr;(&agr;2)j are then fed back to the multipliers, and the multipliers test, during a next clock cycle, the elements &agr;2*(&agr;2)j, (&agr;2)2*(&agr;2)j . . . , (&agr;2)2j and so forth. Similar multipliers also test the odd powers of &agr; as roots of &sgr;′(x)=&sgr;(&agr;x). If P=mn the system may be implemented using a plurality of GF(2m) multipliers. The field GF(2m) is a subfield of GF(2P), and the elements of GF(2P) can each be represented by a combination of n elements of GF(2m). The error locator polynomial &sgr;(x) can thus be represented by a combination of n expressions &sgr;0(x), &sgr;2(x) . . . &sgr;n−1(x), each with coefficients that are elements of GF(2m). Each of the n expressions has 2m−1 coefficients for the terms x0, x1, x2 . . . x2m−1. Thus, n(2m−2) constant GF(2m) multipliers are used to test each element of GF(2P) as a possible root. The number of GF(2m) multipliers in the system is independent of the degree of the error locator polynomial, and each multiplier operates over a subfield of GF(2P). Accordingly, the system can simultaneously tests j elements using j sets of n(2m−2) constant multipliers over GF(2m).

公开(公告)号：US06226772B1

公开(公告)日：2001-05-01

申请号：US09187144

申请日：1998-11-06

Applicant: Lih-Jyh Weng ,  Diana Langer

Inventor： Lih-Jyh Weng ,  Diana Langer

IPC: H03M1300

CPC classification number: H03M13/1555 ,  H03M13/158

Abstract: An n-stage pipelined combined encoder and syndrome generator system includes n stages that are essentially identical. Each of the stages includes two associated delay circuits, namely, a first delay circuit in a chain of feedback adders that operate as a feedback path during encoding, and a second delay circuit in a data input line. During encoding operations, the delay circuits in the feedback adder chain segment the chain of j feedback adders into n stages of j/n adders, and the delay circuits in the data input line delay the data symbols by the latencies associated with the respective stages. The delay circuits thus simultaneously provide to the various stages the corresponding data symbols and propagating sums. After the last data symbol is encoded, the ECC symbols are available after a time lag associated with the j/n adders in the last stage. During syndrome generation operations, the feedback adders are essentially decoupled from one another by AND gates that are included in the feedback path and switches in the data input line bypass the delay circuits, to avoid introducing latency into the syndrome generation operations.

Abstract translation: n级流水线组合编码器和综合征发生器系统包括基本相同的n个阶段。 每个级包括两个相关联的延迟电路，即，在编码期间作为反馈路径工作的反馈加法器链中的第一延迟电路，以及数据输入线中的第二延迟电路。 在编码操作期间，反馈加法器链中的延迟电路将j个反馈加法器链分段成j个加法器的n个级，并且数据输入行中的延迟电路通过与各个级相关联的延迟来延迟数据符号。 因此，延迟电路同时向各个阶段提供对应的数据符号和传播和。 在最后一个数据符号被编码之后，ECC符号在与最后阶段中的j / n加法器相关联的时滞之后可用。 在校正子发生操作期间，反馈加法器基本上通过包括在反馈路径中的AND门和数据输入线中的开关绕过延迟电路彼此解耦，以避免将延迟引入到校正子生成操作中。

公开(公告)号：US5768296A

公开(公告)日：1998-06-16

申请号：US761689

申请日：1996-12-06

Applicant: Diana Langer ,  Michael Leis ,  Cecil Macgregor ,  Lih-Jyh Weng

Inventor： Diana Langer ,  Michael Leis ,  Cecil Macgregor ,  Lih-Jyh Weng

IPC: H03M13/15 ,  H03M13/35 ,  H03M13/00

CPC classification number: H03M13/6516 ,  H03M13/151 ,  H03M13/35

Abstract: A Reed-Solomon error-correction coding (ECC) scheme selectively supports two different-length codes to optimize the trade-off between error performance and the amount of disk space required to store protection symbols. The encoder contains two sets of alpha multipliers; part of one set is multiplexed with the other depending on which code is being used. Also, a shift register within the encoder is selectively lengthened or shortened depending on the code. The code pair is selected so that the generator polynomial of the shorter code is a complete divisor of the generator polynomial of the longer code. Thus, one code is a sub-code of the other. Accordingly, the ECC system is able to use the same syndrome calculator for each code. The error-correction decoder uses those syndromes that correspond to the roots of the generator polynomial of the code being used.

Abstract translation: Reed-Solomon纠错编码（ECC）方案选择性地支持两个不同长度的代码来优化误差性能与存储保护符号所需的磁盘空间量之间的权衡。 编码器包含两组α乘数; 根据正在使用的代码，一组的一部分与另一组复用。 此外，根据代码，编码器内的移位寄存器被选择性地延长或缩短。 选择代码对，使得较短代码的生成多项式是较长代码的生成多项式的完全除数。 因此，一个代码是另一个的子代码。 因此，ECC系统能够对每个代码使用相同的校正子计算器。 纠错解码器使用与所使用代码的生成多项式的根相对应的那些校正子。

公开(公告)号：US5365382A

公开(公告)日：1994-11-15

申请号：US064286

申请日：1993-05-18

Applicant: Lih-Jyh Weng ,  Michael E. Kastner ,  Bruce Leshay

Inventor： Lih-Jyh Weng ,  Michael E. Kastner ,  Bruce Leshay

IPC: G11B20/14 ,  G11B27/30 ,  G11B5/09

CPC classification number: G11B20/1426 ,  G11B27/3027

Abstract: A method and apparatus for identifying and synchronizing to two different fields in a disk drive employs different synchronization or "sync" patterns to reduce the chances of mis-identifying and false-identifying a field. Two very distinct synchronization patterns have been found that satisfy the d=1, k=7 run-length constraints of a data code used in the disk drive. During operation, one sync pattern is searched for to identify and synchronize to its associated field, then the field itself is read. This procedure is then repeated for the other sync pattern and its associated field. Also, the phase of a preamble preceding each sync character is established, so that the number of comparisons needed to find either sync character is reduced. A sync detector operates on cell pairs, and has a selector that selects which sync pattern to search for. The sync detector also has special features that enable it to find preamble and DC Erase fields in the disk cell stream.

Abstract translation: 用于识别和同步到磁盘驱动器中的两个不同字段的方法和装置采用不同的同步或“同步”模式，以减少错误识别和伪识别字段的机会。 已经发现两种非常不同的同步模式满足磁盘驱动器中使用的数据码的d = 1，k = 7游程长度限制。 在操作期间，搜索一个同步模式以识别并同步到其相关联的字段，然后读取字段本身。 然后对其他同步模式及其相关字段重复该过程。 此外，在每个同步字符之前的前导码的相位被建立，使得找到同步字符所需的比较的数量减少。 同步检测器对单元对进行操作，并且具有选择器来选择要搜索的同步模式。 同步检测器还具有使其能够在磁盘单元流中找到前导码和直流擦除字段的特殊功能。

公开(公告)号：US5237574A

公开(公告)日：1993-08-17

申请号：US808035

申请日：1991-12-11

Applicant: Lih-Jyh Weng

Inventor： Lih-Jyh Weng

IPC: G11B20/18 ,  H03M13/29

CPC classification number: G11B20/1883 ,  G11B20/1813 ,  H03M13/29 ,  G11B2220/20

Abstract: A method for determining whether particular information was used in encoding a codeword; the codeword is formed by encoding information as a first preliminary code sequence using a first code and then combining the first preliminary code sequence with a second preliminary code sequence generated using a second code; the particular information is encoded as a desired first preliminary code sequence in accordance with said first code; the desired first preliminary code sequence is then stripped from the codeword to derive a test sequence; the test sequence is decoded in accordance with the second code, and a determination is made, based on the decoding, whether the particular information was used in encoding the codeword. In another aspect, bad sector, servo correction, and sector address values are encoded for storage in a header associated with a sector of storage on a storage medium by encoding the address value with leading zero symbols in accordance with a code having a first rate, encoding the bad sector and servo correction values in a systematic code having a second rate, and combining these sequences to generate a codeword of the first code such that the bad sector and servo correction values appear explicitly in the codeword.

Abstract translation: 一种用于确定在编码码字时是否使用特定信息的方法; 通过使用第一码将信息编码为第一初步码序列，然后将第一初步码序列与使用第二码产生的第二初步码序列组合来形成码字; 所述特定信息根据所述第一代码被编码为期望的第一初步代码序列; 然后从码字中去除期望的第一初步码序列以导出测试序列; 根据第二代码对测试序列进行解码，并且基于解码来确定特定信息是否用于编码码字。 在另一方面，通过根据具有第一速率的代码对具有前导零符号的地址值进行编码，将坏扇区，伺服校正和扇区地址值编码为用于存储在与存储介质上的存储扇区相关联的报头中， 对具有第二速率的系统代码中的坏扇区和伺服校正值进行编码，并组合这些序列以生成第一代码的码字，使得坏扇区和伺服校正值明显地出现在码字中。

公开(公告)号：US5136592A

公开(公告)日：1992-08-04

申请号：US373323

申请日：1989-06-28

Applicant: Lih-Jyh Weng

Inventor： Lih-Jyh Weng

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H04L1/00

CPC classification number: H03M13/15 ,  G11B20/1833

Abstract: The invention is an error detection and correction system which encodes data twice, once for error detection by using a cyclic redundancy check (CRC) code with a generator polynomial, g(x) [in octal form]:g(x)=2413607036565172433223and a second time for error correction by using a Reed-Solomon error correction code. The system then uses the CRC code to check the data for errors. If errors are found the system uses the error location information supplied by the CRC code and the Reed-Solomon code to correct the errors.

公开(公告)号：US4914535A

公开(公告)日：1990-04-03

申请号：US141204

申请日：1988-01-06

Applicant: Lih-Jyh Weng

Inventor： Lih-Jyh Weng

IPC: G11B20/14 ,  G11B20/12 ,  G11B27/10 ,  G11B27/30

CPC classification number: G11B20/1252 ,  G11B27/3027 ,  G11B2220/20

Abstract: The location of the sequence of data bits stored on a storage medium is identified by generating a predetermined synchronization bit sequence; storing on the storage medium a bit sequence corresponding to the predetermined synchronization sequence to indicate the location of the data bit sequence; deriving from the stored corresponding bit sequence on the storage medium a trial sequence; and determining whether the trial sequence corresponds to the predetermined synchronization sequence by determining the number of symbols in which the trial sequence differs from the predetermined synchronization sequence, each symbol comprising a plurality of bits, whereby the effect of clustered bit errors is reduced. The stored data bits are encoded from raw data bits in accordance with a code in which raw data symbols are encoded as data bit groups of at least two different lengths; a bit sequence corresponding to the synchronization sequence is stored on the medium as an indication of the location of the stored data bits; and the synchronization sequence comprises a sequence of raw data symbols which encode as stored encoded groups all of a single length, whereby error propagation is reduced.

Abstract translation: 通过产生预定的同步比特序列来识别存储在存储介质上的数据比特序列的位置; 在所述存储介质上存储与所述预定同步序列相对应的比特序列，以指示所述数据比特序列的位置; 从存储介质上存储的对应比特序列导出试验序列; 以及通过确定所述试验序列与所述预定同步序列不同的符号的数量来确定所述试验序列是否对应于所述预定的同步序列，每个符号包括多个比特，从而降低了聚类比特错误的影响。 存储的数据位根据原始数据符号被编码为至少两个不同长度的数据位组的代码从原始数据位进行编码; 对应于同步序列的位序列作为存储的数据位的位置的指示存储在介质上; 并且同步序列包括原始数据符号序列，其编码为所有单个长度的存储的编码组，由此减小了误差传播。