公开(公告)号：US09270484B2

公开(公告)日：2016-02-23

申请号：US13355575

申请日：2012-01-23

申请人： Charles P. Thacker ,  Andreas G. Nowatzyk ,  Fang Yu ,  Thomas L. Rodeheffer

发明人： Charles P. Thacker ,  Andreas G. Nowatzyk ,  Fang Yu ,  Thomas L. Rodeheffer

IPC分类号： H04L12/437 ,  H04L12/24 ,  H04L12/931 ,  H04L12/913

CPC分类号： H04L12/437 ,  H04L41/0823 ,  H04L41/0893 ,  H04L41/0896 ,  H04L47/724 ,  H04L49/356

摘要： A circuit-based digital communications network is provided for a large data center environment that utilizes circuit switching in lieu of packet switching in order to lower the cost of the network and to gain performance efficiencies. A method for transmitting data in such a network comprises sending a setup request for a path for transmitting the data to a destination node and then speculatively sending the data to the destination node before the setup request is completed.

摘要翻译： 基于电路的数字通信网络被提供用于大数据中心环境，其利用电路交换来代替分组交换，以降低网络的成本并获得性能效率。 一种用于在这样的网络中发送数据的方法包括向目的地节点发送用于发送数据的路径的建立请求，然后在建立请求完成之前将数据推测性地发送到目的地节点。

公开(公告)号：US20130188486A1

公开(公告)日：2013-07-25

申请号：US13355575

申请日：2012-01-23

申请人： Charles P. Thacker ,  Andreas G. Nowatzyk ,  Fang Yu ,  Thomas L. Rodeheffer

发明人： Charles P. Thacker ,  Andreas G. Nowatzyk ,  Fang Yu ,  Thomas L. Rodeheffer

IPC分类号： H04L12/50 ,  H04L12/26

CPC分类号： H04L12/437 ,  H04L41/0823 ,  H04L41/0893 ,  H04L41/0896 ,  H04L47/724 ,  H04L49/356

摘要： A circuit-based digital communications network is provided for a large data center environment that utilizes circuit switching in lieu of packet switching in order to lower the cost of the network and to gain performance efficiencies. A method for transmitting data in such a network comprises sending a setup request for a path for transmitting the data to a destination node and then speculatively sending the data to the destination node before the setup request is completed.

摘要翻译： 基于电路的数字通信网络被提供用于大数据中心环境，其利用电路交换来代替分组交换，以降低网络的成本并获得性能效率。 一种用于在这样的网络中发送数据的方法包括向目的地节点发送用于发送数据的路径的建立请求，然后在建立请求完成之前将数据推测性地发送到目的地节点。

公开(公告)号：US08872800B2

公开(公告)日：2014-10-28

申请号：US13287147

申请日：2011-11-02

申请人： Andreas G. Nowatzyk ,  Charles P. Thacker

发明人： Andreas G. Nowatzyk ,  Charles P. Thacker

IPC分类号： G06F3/042 ,  G06F3/0354 ,  G06F3/03

CPC分类号： G06F3/0325 ,  G06F3/03545

摘要： Optical user input technology comprises three-dimensional (3D) input sensors and 3D location emitters to enable high-precision input in a 3D space, and the 3D location emitter may be a stylus or other writing or pointing device. Certain implementations may comprise an orientation assembly for transmitting orientation of the 3D location emitter in addition to location within a 3D space, and some implementations may also use selectively identifiable signaling from the 3D location emitters to the 3D input sensors to distinguish one 3D location emitter from another, to transmit data other data from a 3D location emitter to a 3D location sensor, or as a means of providing orientation information for the 3D location emitter with respect to the 3D location sensor. Also disclosed are position fixing, indoor navigation, and other complementary applications using 3D input sensors and/or 3D location emitters.

摘要翻译： 光学用户输入技术包括三维（3D）输入传感器和3D位置发射器，以实现3D空间中的高精度输入，并且3D位置发射器可以是触笔或其他写入或指示设备。 某些实施方式可以包括用于发送3D位置发射器的取向以及3D空间内的位置的定向组件，并且一些实施方式还可以使用从3D位置发射器到3D输入传感器的选择性可识别的信令，以区分一个3D位置发射器 另一个，将数据从3D位置发射器传输到3D位置传感器，或者作为相对于3D位置传感器为3D位置发射器提供取向信息的手段。 还公开了位置固定，室内导航和使用3D输入传感器和/或3D位置发射器的其他补充应用。

公开(公告)号：US20130106782A1

公开(公告)日：2013-05-02

申请号：US13287147

申请日：2011-11-02

申请人： Andreas G. Nowatzyk ,  Charles P. Thacker

发明人： Andreas G. Nowatzyk ,  Charles P. Thacker

IPC分类号： G06F3/042 ,  G09G5/00

CPC分类号： G06F3/0325 ,  G06F3/03545

摘要： Optical user input technology comprises three-dimensional (3D) input sensors and 3D location emitters to enable high-precision input in a 3D space, and the 3D location emitter may be a stylus or other writing or pointing device. Certain implementations may comprise an orientation assembly for transmitting orientation of the 3D location emitter in addition to location within a 3D space, and some implementations may also use selectively identifiable signaling from the 3D location emitters to the 3D input sensors to distinguish one 3D location emitter from another, to transmit data other data from a 3D location emitter to a 3D location sensor, or as a means of providing orientation information for the 3D location emitter with respect to the 3D location sensor. Also disclosed are position fixing, indoor navigation, and other complementary applications using 3D input sensors and/or 3D location emitters.

摘要翻译： 光学用户输入技术包括三维（3D）输入传感器和3D位置发射器，以实现3D空间中的高精度输入，并且3D位置发射器可以是触笔或其他写入或指示设备。 某些实施方式可以包括用于发送3D位置发射器的取向以及3D空间内的位置的定向组件，并且一些实施方式还可以使用从3D位置发射器到3D输入传感器的选择性可识别的信令，以区分一个3D位置发射器 另一个，将数据从3D位置发射器传输到3D位置传感器，或者作为相对于3D位置传感器为3D位置发射器提供取向信息的手段。 还公开了位置固定，室内导航和使用3D输入传感器和/或3D位置发射器的其他补充应用。

公开(公告)号：US5088091A

公开(公告)日：1992-02-11

申请号：US370285

申请日：1989-06-22

申请人： Michael D. Schroeder ,  Roger M. Needham ,  Charles P. Thacker ,  Andrew D. Birrell ,  Thomas L. Rodeheffer ,  Edwin H. Satterthwaite, Jr. ,  Hallam G. Murray, Jr.

发明人： Michael D. Schroeder ,  Roger M. Needham ,  Charles P. Thacker ,  Andrew D. Birrell ,  Thomas L. Rodeheffer ,  Edwin H. Satterthwaite, Jr. ,  Hallam G. Murray, Jr.

IPC分类号： H04L12/28 ,  H04L12/44 ,  H04L12/56

CPC分类号： H04L45/00 ,  H04L12/28 ,  H04L45/02 ,  H04L45/16 ,  H04L45/28 ,  H04L45/48 ,  H04L49/351 ,  H04L2012/445 ,  H04L49/101 ,  H04L49/201 ,  H04L49/25 ,  H04L49/251 ,  H04L49/3009

摘要： A mesh connected local area network provides automatic packet switching and routing between host computers coupled to the network. The network has a multiplicity of cut-through, nonblocking switches, each capable of simultaneously routing a multiplicity of data packets. Low host-to-host latency is achieved through the use of cut-through switches with separate internal buffers for each packet being routed. The switches are interconnected with one another and are coupled to the host computers of the network by point to point full duplex links. While each switch can be coupled to ten or more network members, i.e., switches and hosts, each link is coupled to only two network members and is dedicated to carrying signals therebetween. Whenever a new switch or link is added to the network, and whenever a switch or link fails, the switches in the network automatically reconfigure the network by recomputing the set of legal paths through the network.

公开(公告)号：US07571265B2

公开(公告)日：2009-08-04

申请号：US10918364

申请日：2004-08-16

申请人： Charles P. Thacker

发明人： Charles P. Thacker

IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F13/38 ,  H04M1/66 ,  H04M1/68 ,  H04M3/16

CPC分类号： G06F21/88 ,  G06F21/71

摘要： A system and method are provided for reducing a potential thief's motivation to steal an electronic device, by rendering the device inoperative at some time after it is stolen. The mechanism used to deter theft may include a modified primary integrated circuit chip in the electronic device, such as the central processing unit (CPU), a memory controller chip, or a primary input/output (I/O) chip. The chip may be important enough to the normal operation of the electronic device such that without normal operation of the chip, the electronic device also would not operate normally, thus rendering the electronic device partially or fully disabled. A “recharger” device may be used to recharge, or reset the operability of the chip.

摘要翻译： 提供了一种系统和方法，用于通过使设备在被盗后的某个时间不起作用，减少潜在窃贼窃取电子设备的动机。 用于防止盗窃的机制可以包括电子设备中的修改的主要集成电路芯片，例如中央处理单元（CPU），存储器控制器芯片或主要输入/输出（I / O）芯片。 芯片对于电子设备的正常操作可能是足够重要的，使得如果没有芯片的正常操作，电子设备也将不能正常地操作，从而使电子设备部分地或完全地被禁用。 可以使用“充电器”装置对芯片的可操作性进行再充电或复位。

公开(公告)号：US5136700A

公开(公告)日：1992-08-04

申请号：US454922

申请日：1989-12-22

申请人： Charles P. Thacker

发明人： Charles P. Thacker

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0811

摘要： In a multiprocessor computer system, a number of processors are coupled to main memory by a shared memory bus, and one or more of the processors have a two level direct mapped cache memory. When any one processor updates data in a shared portion of the address space, a cache check request signal is transmitted on the shared data bus, which enables all the cache memories to update their contents if necessary. Since both caches are direct mapped, each line of data stored in the first cache is also stored in one of the blocks in the second cache. Each cache has control logic for determining when a specified address location is stored in one of its lines or blocks. To avoid spurious accesses to the first level cache when a cache check is performed, the second cache has a special table which stores a pointer for each line in said first cache array. This pointer denotes the block in the second cache which stores the same data as is stored in the corresponding line of the first cache. When the control logic of the second cache indicates that the specified address for a cache check is located in the second cache, a lookup circuit compares the pointer in the special table which corresponds to the specified address with a subset of the bits of the specified address. If the two match, then the specified address is located in the first cache, and the first cache is updated.

公开(公告)号：US5301283A

公开(公告)日：1994-04-05

申请号：US870134

申请日：1992-04-16

申请人： Charles P. Thacker ,  David Hartwell

发明人： Charles P. Thacker ,  David Hartwell

IPC分类号： G06F13/36 ,  G06F13/368 ,  G06F13/00

CPC分类号： G06F13/36 ,  G06F13/368

摘要： In a data processing system having a plurality of commander nodes and at least one resource node interconnected by a system bus, a bus arbitration technique determines which commander node is to gain control of the system bus to access the resource node. The bus arbitration technique assigns priority levels to all commander nodes, with at least one commander node receiving more than one priority level. Each priority level has an associated signal path. During each arbitration, each contending commander node can activate or assert the signal path associated with its priority level, and the commander node having more than one priority level can assert the signal path associated with any one of its priority levels. All commander nodes monitor all the signal paths to determine the identity of the contending commander node that asserted the signal path associated with the highest priority level among those that were asserted, and, thus, the contending commander node that "won" the arbitration.

摘要翻译： 在具有多个命令器节点和由系统总线互连的至少一个资源节点的数据处理系统中，总线仲裁技术确定哪个命令器节点获得系统总线的控制以访问资源节点。 总线仲裁技术为所有指挥员节点分配优先级，至少有一个指挥官节点接收多个优先级。 每个优先级具有相关联的信号路径。 在每个仲裁期间，每个竞争指挥官节点可以激活或断言与其优先级相关联的信号路径，并且具有多于一个优先级的指令器节点可以断言与其优先级中的任何一个相关联的信号路径。 所有指挥员节点都监视所有的信号路径，以确定有争议的指挥官节点的身份，该指挥官节点断言与被断言的那些信号路由最高优先级相关联的信号路径，因此，竞争指挥官节点“赢得”仲裁。

公开(公告)号：US5193197A

公开(公告)日：1993-03-09

申请号：US576177

申请日：1990-08-30

申请人： Charles P. Thacker

发明人： Charles P. Thacker

IPC分类号： G06F13/16

CPC分类号： G06F13/1605

摘要： In a data processing system in which resource units are shared by a plurality of processing units, an arbitration unit is disclosed wherein the priority assigned to each processing unit is dynamically assigned to equalize accessibility to the shared resource. A signal path, associated with each possible level of priority, is coupled to each processor unit. The processor unit applies an activation signal to the signal line associated with the priority of the processing unit when the processing unit has a requirement for the shared resource and an arbitration is being performed to determine access to the resource. During the arbitration procedure, each processing unit requiring access to the shared resource compares the current priority of the associated processing unit to the activation signals on the signal paths to determine when the processing unit can gain access to the shared resource. After the arbitration procedure, the processing unit priority level is redetermined by each processing unit based on a comparison of the current priority level and the highest priority level active during arbitration.

摘要翻译： 在其中资源单元由多个处理单元共享的数据处理系统中，公开了一种仲裁单元，其中分配给每个处理单元的优先级被动态分配以均衡对共享资源的可访问性。 与每个可能的优先级相关联的信号路径被耦合到每个处理器单元。 当处理单元具有对共享资源的要求并且正在执行仲裁以确定对资源的访问时，处理器单元将激活信号施加到与处理单元的优先级相关联的信号线。 在仲裁过程中，需要访问共享资源的每个处理单元将相关处理单元的当前优先级与信号路径上的激活信号进行比较，以确定处理单元何时可以访问共享资源。 在仲裁程序之后，基于当前优先级与仲裁期间活动的最高优先级的比较，每个处理单元重新确定处理单元优先级。

公开(公告)号：US4148098A

公开(公告)日：1979-04-03

申请号：US806781

申请日：1977-06-15

申请人： Edward M. McCreight ,  Charles P. Thacker

发明人： Edward M. McCreight ,  Charles P. Thacker

IPC分类号： G06F3/06 ,  G06F13/12 ,  G11B20/18 ,  G06F11/00 ,  G06F13/00

CPC分类号： G06F3/0601 ,  G06F13/122 ,  G11B20/18 ,  G06F2003/0692

摘要： A data processing system includes a disk drive, a disk drive controller, a main memory and a CPU. The main memory has disk command data stored therein in a chain of disk command blocks (DCB's). Each DCB contains a first word pointing to the next DCB in the chain, a second word containing status information and a third word containing command information. A portion of the command word contains a predetermined verification word when the DCB is valid. The CPU includes means for comparing this portion with the predetermined verification word as stored in a constant memory. If the two correspond, the DCB is valid. Each DCB also includes a fourth word pointing to a block of main memory in which header data is stored. Header data defines the address of the recording location of the disk. A fifth word points to a block of main memory in which label data is stored. Label data defines the name and/or number of the file, as well as itself including a pointer to the address location on the disk at which the next page of the file data is stored. A sixth word of the DCB points to a block of main memory in which the associated page of file data is stored. A seventh word specifies the recording location on the disk (drive, track, sector) where the actions specified in the command word are to be carried out. Each such recording location is capable of having stored therein the header, label and file data associated with a specific DCB.

摘要翻译： 数据处理系统包括磁盘驱动器，磁盘驱动器控制器，主存储器和CPU。 主存储器具有存储在一盘盘命令块（DCB）中的盘命令数据。 每个DCB包含指向链中下一个DCB的第一个字，包含状态信息的第二个字和包含命令信息的第三个字。 当DCB有效时，命令字的一部分包含预定的验证字。 CPU包括用于将该部分与存储在恒定存储器中的预定验证字进行比较的装置。 如果两者对应，则DCB有效。 每个DCB还包括指向存储头部数据的主存储器块的第四字。 标题数据定义磁盘记录位置的地址。 第五个字指向存储标签数据的主存储器块。 标签数据定义文件的名称和/或编号，以及其自身，包括指向存储文件数据的下一页的磁盘上的地址位置的指针。 DCB的第六个字指向存储相关页面的主存储器块。 第七个字指定要执行命令字中指定的动作的磁盘（驱动器，磁道，扇区）上的记录位置。 每个这样的记录位置能够存储与特定DCB相关联的标题，标签和文件数据。