公开(公告)号：US5923075A

公开(公告)日：1999-07-13

申请号：US630706

申请日：1996-04-08

申请人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Pom Suan Tan

发明人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Pom Suan Tan

IPC分类号： H01L27/118 ,  H01L29/00

CPC分类号： H01L27/11803 ,  Y10S438/922

摘要： A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

摘要翻译： 描述了在限定反熔丝窗口中使用未掺杂的多晶硅膜作为掩模来制造抗熔丝电池的方法。 在半导体衬底的表面上设置一层氧化硅。 第一未掺杂的多晶硅层沉积在氧化硅层上。 第一未掺杂的多晶硅层被图案化以形成掩模的光致抗蚀剂层覆盖。 将第一未掺杂的多晶硅层和一部分氧化硅层蚀刻掉，其中它们不被掩模覆盖以形成电池开口。 除去孔中的掩模和剩余的氧化硅。 绝缘层沉积在第一未掺杂多晶硅层的表面上并且在电池开口内。 第二多晶硅层沉积在绝缘层上并掺杂。 将第二多晶硅层图案化以形成抗熔丝电池。 形成栅电极和源极和漏极区，完成集成电路器件的制造。

公开(公告)号：US06307248B1

公开(公告)日：2001-10-23

申请号：US09289890

申请日：1999-04-12

申请人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

发明人： Che-Chia Wei ,  Lap Chan ,  Bob Lee ,  Poh Suan Tan

IPC分类号： H01L2900

CPC分类号： H01L27/11803 ,  Y10S438/922

摘要： A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

摘要翻译： 描述了在限定反熔丝窗口中使用未掺杂的多晶硅膜作为掩模来制造抗熔丝电池的方法。 在半导体衬底的表面上设置一层氧化硅。 第一未掺杂的多晶硅层沉积在氧化硅层上。 第一未掺杂的多晶硅层被图案化以形成掩模的光致抗蚀剂层覆盖。 将第一未掺杂的多晶硅层和一部分氧化硅层蚀刻掉，其中它们不被掩模覆盖以形成电池开口。 除去孔中的掩模和剩余的氧化硅。 绝缘层沉积在第一未掺杂多晶硅层的表面上并且在电池开口内。 第二多晶硅层沉积在绝缘层上并掺杂。 将第二多晶硅层图案化以形成抗熔丝电池。 形成栅电极和源极和漏极区，完成集成电路器件的制造。

公开(公告)号：US5610083A

公开(公告)日：1997-03-11

申请号：US650697

申请日：1996-05-20

申请人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

发明人： Lap Chan ,  Ravis H. Sundaresan ,  Che-Chia Wei

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203

摘要： A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

摘要翻译： 已经开发了用于在SOI层中产生可以容易地并入MOSFET制造配方中的背栅极接触的工艺。 背栅极接触由蚀刻的沟槽组成，内衬绝缘体并填充有多晶硅。 多晶硅填充沟槽将半导体衬底电连接到覆盖的金属触点。

公开(公告)号：US5677238A

公开(公告)日：1997-10-14

申请号：US638667

申请日：1996-04-29

申请人： Fang Hong Gn ,  Sekar Ramamoorthy ,  Lap Chan ,  Che-Chia Wei

发明人： Fang Hong Gn ,  Sekar Ramamoorthy ,  Lap Chan ,  Che-Chia Wei

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/283

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843

摘要： A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.

摘要翻译： 已经开发了用于制造硅中的有源器件区域与覆盖金属化水平之间的改进连接的方法。 该方法产生具有优异和改善的屏障完整性的触点，其允许硅器件暴露于延长的热处理时间和/或较高温度过程，而不会金属渗入硅接触接合区域。 关键元素是在多层阻挡结构中添加共形CVD钨层。

公开(公告)号：US5624871A

公开(公告)日：1997-04-29

申请号：US699222

申请日：1996-08-19

申请人： Yeow M. Teo ,  Kah S. Seah ,  Lap Chan ,  Che-Chia Wei

发明人： Yeow M. Teo ,  Kah S. Seah ,  Lap Chan ,  Che-Chia Wei

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76895 ,  H01L21/76889 ,  Y10S438/934

摘要： A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.

摘要翻译： 在半导体器件上制造互连的方法具有含硅的导电表面和电介质表面。 该方法包括在含硅导电表面上形成覆盖的第一难熔金属硅化物的分开的区域，第一难熔金属硅化物由表面上的第一难熔金属和硅组成，在该器件上形成毯状的第二难熔金属层，形成 在第二耐火金属层上方的覆盖的α-Si层，在器件上形成掩模以对分离区域之间的互连进行图案化，然后蚀刻掉难熔金属层和α-Si层的不需要的部分，执行快速热 在α-Si层和第二难熔金属层之间形成低电阻难熔金属硅化物的器件上的退火工艺，然后蚀刻除了难熔金属硅化物不被覆盖的难熔金属层的不希望的部分。

公开(公告)号：US06617242B1

公开(公告)日：2003-09-09

申请号：US08480543

申请日：1995-06-07

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

IPC分类号： H01L2144

CPC分类号： H01L21/76858 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

摘要翻译： 在半导体集成电路中制造层间接触的方法提供通过绝缘层形成接触开口。 一层难熔金属或难熔金属合金沉积在集成电路芯片的表面上。 然后在显着提高的温度下沉积铝层，使得在铝层和难熔金属层之间的界面处形成铝/难熔金属合金。 这种合金的形成导致接触开口内的金属膨胀，从而填充接触开口并为沉积的铝层提供光滑的上部轮廓。

公开(公告)号：US06242811B1

公开(公告)日：2001-06-05

申请号：US09080066

申请日：1998-05-15

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/28512 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

摘要翻译： 通过形成通过绝缘层的接触开口来制造半导体集成电路中的层间接触。 一层难熔金属或难熔金属合金沉积在集成电路芯片的表面上。 然后在显着提高的温度下沉积铝层，使得在铝层和难熔金属层之间的界面处形成铝/难熔金属合金。 这种合金的形成导致接触开口内的金属膨胀，从而填充接触开口并为沉积的铝层提供光滑的上部轮廓。

公开(公告)号：US6159836A

公开(公告)日：2000-12-12

申请号：US438099

申请日：1995-05-08

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

摘要翻译： 提供了可编程半导体接触结构和方法。 半导体衬底具有用于形成互连的第一图案化导电层。 第一绝缘层覆盖在第一图案化导电层上。 通过绝缘层形成开口到第一图案化导电层以形成接触通孔。 缓冲层覆盖第一绝缘层的部分并覆盖开口。 第二导电层覆盖缓冲层。 然后第三导电层覆盖集成电路。 缓冲层是诸如非晶硅的材料，其用作抗熔丝并且可以通过应用相对高的编程电压进行编程。

公开(公告)号：US5500382A

公开(公告)日：1996-03-19

申请号：US293140

申请日：1994-08-19

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76897

摘要： A method for forming a self-aligned contact utilizes a thin insulating layer formed on the upper surface of a conductive layer. A barrier layer is deposited over the insulating layer, and gate electrodes are then defined. Sidewall spacers are formed along the vertical sidewalls of the gate electrodes. During formation of the sidewall spacers the barrier layer protects the gate electrodes. A second insulating layer is then deposited and a via is opened to the substrate. A contact can now be created by depositing conductive material into the via.

摘要翻译： 用于形成自对准接触的方法利用形成在导电层的上表面上的薄绝缘层。 在绝缘层上沉积阻挡层，然后限定栅电极。 沿着栅电极的垂直侧壁形成侧壁间隔物。 在形成侧壁间隔物期间，阻挡层保护栅电极。 然后沉积第二绝缘层，并且通孔向基板开口。 现在可以通过将导电材料沉积到通孔中来形成接触。

公开(公告)号：US5326724A

公开(公告)日：1994-07-05

申请号：US815312

申请日：1991-12-27

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L21/28518 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S438/902 ,  Y10S438/97

摘要： A titanium nitride layer is deposited between the metal titanium layer and the oxide cap of a conventional oxide capped titanium disilicide technology process. This titanium nitride layer is deposited in-situ after a certain thickness of metal titanium has been deposited by bleeding nitrogen gas into the titanium sputter machine. Thereafter the normal oxide cap is deposited over this titanium nitride layer. The normal titanium react process is performed to produce titanium disilicide. After the titanium disilicide has been produced, it is then necessary to strip off the oxide cap. The extra titanium nitride layer makes it is possible to use a wet etch to remove the oxide cap, with the titanium nitride layer serving as a etch stop. In this manner an isotropic wet etch may be employed to remove all of the oxide cap layer. The isotropic wet etch is preferably a 10% buffered HF etch.

摘要翻译： 在常规氧化物封端的二硅化钛工艺工艺的金属钛层和氧化物盖之间沉积氮化钛层。 在通过将氮气渗入钛溅射机中沉积了一定厚度的金属钛之后，该氮化钛层原位沉积。 此后，在该氮化钛层上沉积正常氧化物盖。 进行正常的钛反应工艺以生产二硅化钛。 在制造二硅化钛后，需要剥离氧化物盖。 额外的氮化钛层使得可以使用湿蚀刻去除氧化物盖，其中氮化钛层用作蚀刻停止。 以这种方式，可以采用各向同性的湿蚀刻来去除所有氧化物盖层。 各向同性湿蚀刻优选为10％缓冲的HF蚀刻。