公开(公告)号：US08601198B2

公开(公告)日：2013-12-03

申请号：US13174436

申请日：2011-06-30

申请人： Chee Hak Teh ,  Chai Huat Gan ,  Poh Thiam Teoh ,  Mary Siaw See Yeoh ,  Su Wei Lim

发明人： Chee Hak Teh ,  Chai Huat Gan ,  Poh Thiam Teoh ,  Mary Siaw See Yeoh ,  Su Wei Lim

IPC分类号： G06F13/20 ,  G06F13/38

CPC分类号： G06F13/385 ,  G06F13/4022

摘要： Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router.Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.

摘要翻译： 本发明的实施例描述了能够将PCIe设备和另一单独的设备关联到相同设备标识符（例如，设备号码）的主机系统。 周期路由模块或逻辑将识别涉及设备标识符的I / O事务，并将事务路由到一个或两个设备（或者在某些情况下，将I / O事务标识为配置事务，并且简单地更新 循环路由模块/逻辑）。 在本发明的一个实施例中，主机系统的根端口被配置为作为上述循环路由器进行操作。 本发明的实施例允许将设备“合并”成用于主机OS的单个设备。 例如，经由PCIe链路耦合到主机系统的外围设备可以经由另一PCIe链路或SATA链路与耦合到主机系统的外围设备“合并”。

公开(公告)号：US20130007332A1

公开(公告)日：2013-01-03

申请号：US13174436

申请日：2011-06-30

申请人： Chee Hak Teh ,  Chai Huat Gan ,  Poh Thiam Teoh ,  Mary Siaw See Yeoh ,  Su Wei Lim

发明人： Chee Hak Teh ,  Chai Huat Gan ,  Poh Thiam Teoh ,  Mary Siaw See Yeoh ,  Su Wei Lim

IPC分类号： G06F13/20

CPC分类号： G06F13/385 ,  G06F13/4022

摘要： Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router.Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.

摘要翻译： 本发明的实施例描述了能够将PCIe设备和另一单独的设备关联到相同设备标识符（例如，设备号码）的主机系统。 周期路由模块或逻辑将识别涉及设备标识符的I / O事务，并将事务路由到一个或两个设备（或者在某些情况下，将I / O事务标识为配置事务，并且简单地更新 循环路由模块/逻辑）。 在本发明的一个实施例中，主机系统的根端口被配置为作为上述循环路由器进行操作。 本发明的实施例允许将设备合并到用于主机OS的单个设备中。 例如，经由PCIe链路耦合到主机系统的外围设备可以与经由另一PCIe链路或SATA链路耦合到主机系统的外围设备合并。

公开(公告)号：US07502377B2

公开(公告)日：2009-03-10

申请号：US10976682

申请日：2004-10-29

申请人： Su Wei Lim ,  Chai Huat Gan ,  Darren L. Abramson

发明人： Su Wei Lim ,  Chai Huat Gan ,  Darren L. Abramson

IPC分类号： H04L12/28 ,  H04J3/16

CPC分类号： G06F13/4027

摘要： In embodiments of the present invention, a PCI bus to PCE Express protocol conversion module includes a process implemented by control logic to convert streaming PCI information to PCI Express packets. In one embodiment, an agent may transfer PCI data and associated byte enables to a first queue, which may temporarily store the PCI data and associated byte enables in a quad word format. A decoder may determine whether the PCI byte enables are combinable, contiguous, and/or active, and, using state machines, transfer a quantity of the PCI data and associated byte enables from the first queue to a second larger queue. The state machines may break the PCI stream to arrive at the quantity of PCI data being transferred. The second queue may have at least one location to temporarily store the quantity of data and byte enables in at least one packet having a PCI express format.

摘要翻译： 在本发明的实施例中，PCI总线到PCE Express协议转换模块包括由控制逻辑实现的流程，以将流式PCI信息转换成PCI Express分组。 在一个实施例中，代理可以将PCI数据和相关联的字节启用转移到第一队列，其可以临时存储PCI数据和相关字节使能为四字格式。 解码器可以确定PCI字节使能是否是可组合的，连续的和/或活动的，并且使用状态机将数量的PCI数据和相关联的字节启用从第一队列传送到第二较大队列。 状态机可能会中断PCI流以达到正在传输的PCI数据量。 第二队列可以具有至少一个位置来临时存储具有PCI表达格式的至少一个分组中的数据量和字节使能。

公开(公告)号：US08560764B2

公开(公告)日：2013-10-15

申请号：US12643131

申请日：2009-12-21

申请人： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Rover, Jr. ,  Chai Huat Gan

发明人： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Rover, Jr. ,  Chai Huat Gan

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G11C16/10 ,  G11C16/32

摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

公开(公告)号：US07724645B2

公开(公告)日：2010-05-25

申请号：US11476252

申请日：2006-06-27

申请人： Serge R. Bedwani ,  Soon Seng Seh ,  Siang Lin Tan ,  Amber Huffman ,  Chai Huat Gan

发明人： Serge R. Bedwani ,  Soon Seng Seh ,  Siang Lin Tan ,  Amber Huffman ,  Chai Huat Gan

IPC分类号： H04J1/16

CPC分类号： G06F11/24

摘要： An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.

摘要翻译： 描述了用于串行链路下行检测的装置和方法。 在一个实施例中，该方法包括检测串行链路的初始链路断开状态。 在一个实施例中，例如当在接收器输入处检测到从正常信令电压电平到静噪信令电压电平的转变时，检测到初始链路断开状态。 当检测到初始链路断开状态时，从串行链路上的静噪电压的检测开始，链路降低信号的发出被延迟预定的时间段。 在一个实施例中，如果在从静噪电压的检测出来的预定时间段之后检测到数据错误，则断开链路信号。 描述和要求保护其他实施例。

公开(公告)号：US07620833B2

公开(公告)日：2009-11-17

申请号：US11633183

申请日：2006-12-04

申请人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

发明人： Chai Huat Gan ,  Darren Abramson ,  Zohar Bogin

IPC分类号： G06F1/32

CPC分类号： G06F1/3225

摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.

摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。

公开(公告)号：US06854045B2

公开(公告)日：2005-02-08

申请号：US09895691

申请日：2001-06-29

申请人： Eng Hun Ooi ,  Thien Ern Ooi ,  Chai Huat Gan

发明人： Eng Hun Ooi ,  Thien Ern Ooi ,  Chai Huat Gan

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F3/0632 ,  G06F3/0607 ,  G06F3/0674

摘要： An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

摘要翻译： 访问检测器检测对与串行存储设备接口的多个串行端口中的一个的访问的访问类型。 该访问旨在经由并行通道的任务文件寄存器与并行存储设备接口的多个并行通道之一。 映射电路将串行端口映射到并行通道。 状态机根据访问类型和映射的串行端口仿真来自并行通道之一的响应。

公开(公告)号：US20140019676A1

公开(公告)日：2014-01-16

申请号：US14024724

申请日：2013-09-12

申请人： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Royer, JR. ,  Chai Huat Gan

发明人： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Royer, JR. ,  Chai Huat Gan

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G11C16/10 ,  G11C16/32

摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

摘要翻译： 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。

公开(公告)号：US20110153914A1

公开(公告)日：2011-06-23

申请号：US12643131

申请日：2009-12-21

申请人： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Royer, JR. ,  Chai Huat Gan

发明人： Amber D. Huffman ,  Suryaprasad Kareenahalli ,  Robert J. Royer, JR. ,  Chai Huat Gan

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G11C16/10 ,  G11C16/32

摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.

摘要翻译： 控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。 响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。

公开(公告)号：US20080301397A1

公开(公告)日：2008-12-04

申请号：US11807694

申请日：2007-05-30

申请人： Chee How Goh ,  Eric Thian Aun Tan ,  Chai Huat Gan

发明人： Chee How Goh ,  Eric Thian Aun Tan ,  Chai Huat Gan

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/7201 ,  G06F2212/7203

摘要： A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag.

摘要翻译： 这里公开了利用NAND型存储器的方法。 可由处理器执行的操作系统类型指令可以存储在基于NAND的存储器中。 指令可以具有可由处理器利用以获取操作系统指令的逻辑地址。 该方法可以将地址转换存储在基于NAND的存储器中，其中地址转换可将逻辑地址与物理地址相关联。 至少一个有效标志可以分配给地址转换。 响应于有效标志的第一设置，处理器可以执行来自基于NAND的存储器的操作系统指令的直接读取，并且处理器可以通过从基于NAND的存储器获取地址转换来执行操作系统指令的间接读取 响应于所述至少一个有效性标志的第二设置。