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    Method and apparatus for clock frequency ratio independent error logging
    2.
    发明授权
    Method and apparatus for clock frequency ratio independent error logging 有权
    时钟频率比独立误差测井的方法和装置

    公开(公告)号：US09489008B2

    公开(公告)日：2016-11-08

    申请号：US13976933

    申请日：2011-12-22

    申请人： Ming Yi Lim ,  Su Wei Lim ,  Poh Thiam Teoh

    发明人： Ming Yi Lim ,  Su Wei Lim ,  Poh Thiam Teoh

    IPC分类号： G11C29/00 ,  G06F1/10 ,  G06F13/00 ,  G06F11/08 ,  G06F11/10

    CPC分类号： G06F1/10 ,  G06F11/08 ,  G06F11/1004 ,  G06F13/00

    摘要： A method and system for error logging that is independent of the clock frequency ratio in an I/O subsystem. In one embodiment of the invention, the I/O subsystem has an error logging mechanism with a fixed queue depth of two and is independent of the clock frequencies in the I/O subsystem. The I/O subsystem has two queue entries for storing or logging the uncorrectable errors. In one embodiment of the invention, the I/O subsystem has two queue entries for storing or logging the 128-bit TLP Header and the First Error Pointer (FEP) of the uncorrectable errors detected in the I/O subsystem.

    摘要翻译： 一种独立于I / O子系统时钟频率比的错误记录方法和系统。 在本发明的一个实施例中，I / O子系统具有错误记录机制，其固定的队列深度为2，独立于I / O子系统中的时钟频率。 I / O子系统有两个队列条目用于存储或记录不可纠正的错误。 在本发明的一个实施例中，I / O子系统具有用于存储或记录在I / O子系统中检测到的不可校正错误的128位TLP头和第一错误指针（FEP）的两个队列条目。

    BAND DYNAMIC SWITCHING BETWEEN TWO BUS STANDARDS
    4.
    发明申请
    BAND DYNAMIC SWITCHING BETWEEN TWO BUS STANDARDS 审中-公开
    两个总线标准之间的带动态切换

    公开(公告)号：US20140181356A1

    公开(公告)日：2014-06-26

    申请号：US14194893

    申请日：2014-03-03

    申请人： Ting Lok Song ,  Su Wei Lim ,  Mikal Hunsaker ,  Hooi Kar Loo

    发明人： Ting Lok Song ,  Su Wei Lim ,  Mikal Hunsaker ,  Hooi Kar Loo

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

    摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

    摘要翻译： 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

    Architected Protocol For Changing Link Operating Mode
    5.
    发明申请
    Architected Protocol For Changing Link Operating Mode 有权

    公开(公告)号：US20140003451A1

    公开(公告)日：2014-01-02

    申请号：US13718067

    申请日：2012-12-18

    申请人： Mahesh Wagh ,  Su Wei Lim

    发明人： Mahesh Wagh ,  Su Wei Lim

    IPC分类号： H04L12/24

    CPC分类号： G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

    摘要： In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

    METHOD AND APPARATUS FOR AGENT INTERFACING WITH PIPELINE BACKBONE TO LOCALLY HANDLE TRANSACTIONS WHILE OBEYING ORDERING RULE
    6.
    发明申请
    METHOD AND APPARATUS FOR AGENT INTERFACING WITH PIPELINE BACKBONE TO LOCALLY HANDLE TRANSACTIONS WHILE OBEYING ORDERING RULE 有权
    在管理订单规则下，与管道底板接口进行本地手柄交易的方法和装置

    公开(公告)号：US20130283013A1

    公开(公告)日：2013-10-24

    申请号：US13997628

    申请日：2011-11-09

    申请人： Ngek Leong Guok ,  Kah Meng Yeem ,  Poh Thiam Teoh ,  Su Wei Lim

    发明人： Ngek Leong Guok ,  Kah Meng Yeem ,  Poh Thiam Teoh ,  Su Wei Lim

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30043 ,  G06F13/14 ,  G06F15/163 ,  H04L69/12

    摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule including, for example, receiving a transaction which requests access to a backbone; decoding routing destination information from the transaction received, in which the decoded routing destination information designates the transaction to be processed either locally or processed via the backbone; storing the decoded routing destination information and the transaction into a First-In-First-Out (FIFO) buffer; retrieving the decoded routing destination information and the transaction from the FIFO buffer; and processing the transaction locally or via the backbone based on the decoded routing destination information retrieved from the FIFO buffer with the transaction.

    摘要翻译： 根据本文公开的实施例，提供了用于使得代理与流水线骨干网接口的本地处理事务的方法，系统和装置，同时服从排序规则，包括例如接收请求访问主干的事务; 从所接收的事务解码路由目的地信息，其中解码的路由目的地信息指定要在本地处理或经由骨干处理的交易; 将解码的路由目的地信息和交易存储到先进先出（FIFO）缓冲器中; 从FIFO缓冲器检索解码的路由目的地信息和事务; 以及基于从所述事务处理从所述FIFO缓冲器检索的解码的路由目的地信息，在本地或经由所述主干处理所述事务。

    Effective caching mechanism with programmable resource dedication
    7.
    发明申请
    Effective caching mechanism with programmable resource dedication 有权
    有效的缓存机制，可编程资源的奉献

    公开(公告)号：US20080005513A1

    公开(公告)日：2008-01-03

    申请号：US11480669

    申请日：2006-06-30

    申请人： Su Wei Lim

    发明人： Su Wei Lim

    IPC分类号： G06F12/14 ,  G06F12/00

    CPC分类号： G06F12/0875 ,  G06F12/1425

    摘要： A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection information stored in a cache. The cache is shared by the bus masters and allocation of the cache entries is prioritized among the bus masters.

    摘要翻译： 系统包括多个总线主机，其生成访问被保护的存储器设备的直接存储器访问请求。 在授予访问权限之前，系统会检查存储在缓存中的内存保护信息。 高速缓存由总线主机共享，高速缓存条目的分配在总线主机之间是优先的。

    Power mangement techniques for an input/output (I/O) subsystem
    9.
    发明授权
    Power mangement techniques for an input/output (I/O) subsystem 有权
    输入/输出（I / O）子系统的电力管理技术

    公开(公告)号：US09270555B2

    公开(公告)日：2016-02-23

    申请号：US13175557

    申请日：2011-07-01

    申请人： Poh Thiam Teoh ,  Su Wei Lim

    发明人： Poh Thiam Teoh ,  Su Wei Lim

    IPC分类号： H04L12/26 ,  H04L12/12

    CPC分类号： H04L43/0876 ,  H04L12/12 ,  H04L43/0882 ,  Y02B60/1235 ,  Y02D50/40

    摘要： A method and system to improve the power management for an I/O subsystem. In one embodiment of the invention, the power management of an upstream port of the I/O subsystem is improved by increasing the upstream link utilization when the upstream port is an active power state and by increasing or prolonging the power saving period of the upstream port when the upstream port is in a low power state.

    摘要翻译： 一种改进I / O子系统电源管理的方法和系统。 在本发明的一个实施例中，通过在上游端口是有功功率状态时增加上游链路利用率，并且通过增加或延长上游端口的节电周期来提高I / O子系统的上行端口的功率管理 当上游端口处于低功率状态时。