公开(公告)号：US08633730B1

公开(公告)日：2014-01-21

申请号：US13588435

申请日：2012-08-17

申请人： Chen W. Tseng ,  Weiguang Lu ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Aditya Chaubal ,  Derrick S. Woods

发明人： Chen W. Tseng ,  Weiguang Lu ,  William W. Stiehl ,  Robert M. Balzli, Jr. ,  Carl M. Stern ,  Aditya Chaubal ,  Derrick S. Woods

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F1/24 ,  G06F17/50

CPC分类号： H03K19/17768 ,  G06F1/24 ,  G06F1/3287 ,  H03K19/17708 ,  Y02D10/171 ,  Y02D50/20

摘要： When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.

摘要翻译： 当可编程集成电路（“IC”）的第一子电路要被去激活时，全局写使能（GWE）信号被断言。 响应于GWE信号的取消取消和与第一子电路处于第一状态相关联的第一存储单元，第一子电路中的触发器被禁止改变状态。 响应于与第一子电路以外的子电路相关联的存储器单元处于第二状态，其他子电路中的触发器能够改变状态。 当第一个子电路被激活时，GWE信号被断言。 由第一子电路实现的逻辑在GWE信号的解除和断言之间得以保留。 响应于GWE信号的断言和与第一子电路处于第一状态相关联的第一存储单元，第一子电路中的触发器能够改变状态。

公开(公告)号：US08286113B1

公开(公告)日：2012-10-09

申请号：US13004183

申请日：2011-01-11

申请人： Brendan K. Bridgford ,  Jason J. Moore ,  W. Story Leavesley, III ,  Derrick S. Woods

发明人： Brendan K. Bridgford ,  Jason J. Moore ,  W. Story Leavesley, III ,  Derrick S. Woods

IPC分类号： G06F17/50 ,  G06F15/177 ,  G06F9/00

CPC分类号： G06F17/5022 ,  G06F17/5054 ,  G06F2217/66

摘要： A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.

摘要翻译： 提供了一种用于验证完整比特流中的逻辑核的实现的系统和方法。 从完整比特流中提取逻辑核心比特流。 将逻辑核心比特流与用于目标设备的逻辑核心的参考比特流进行比较。 响应于逻辑核心比特流和参考比特流的比较中没有差异，存储指示包含在完整比特流中的逻辑核心实现被验证的数据值。