公开(公告)号：US5472894A

公开(公告)日：1995-12-05

申请号：US294569

申请日：1994-08-23

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8234

CPC分类号： H01L29/7834 ,  H01L29/66621 ,  Y10S257/90

摘要： A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers, improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

摘要翻译： 描述了轻掺杂漏极（LDD）晶体管器件结构及其制造方法。 提供了在其中形成有沟槽的硅衬底。 在沟槽的侧壁上形成多晶硅侧壁间隔物。 二氧化硅侧壁间隔物形成在多晶硅侧壁间隔物的侧壁上。 通过氧化在沟槽的底部形成栅极氧化层。 形成填充沟槽的多晶硅栅极层。 将杂质注入到硅衬底中以在硅衬底的与多晶硅侧壁间隔物相邻的间隔开的部分中同时形成重掺杂的源极/漏极区，改善多晶硅栅极层的导电性，并形成间隔开的轻掺杂源极/漏极区 在二氧化硅侧壁间隔下的硅衬底的分开的部分。

公开(公告)号：US5616946A

公开(公告)日：1997-04-01

申请号：US597542

申请日：1996-04-25

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L27/112

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/91 ,  Y10S438/981

摘要： A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

摘要翻译： 已经开发了用于制造只读存储器（ROM），器件的方法。 该ROM器件的可编程单元由P / N二极管组成，位于N +掩埋位线中。 二极管形成是通过使用来自P +多晶硅字线的外扩散实现的，其与特定位线区域直接接触。

公开(公告)号：US5550075A

公开(公告)日：1996-08-27

申请号：US374967

申请日：1995-01-19

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L21/265

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/91 ,  Y10S438/981

摘要： A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

摘要翻译： 已经开发了用于制造只读存储器（ROM），器件的方法。 该ROM器件的可编程单元由P / N二极管组成，位于N +掩埋位线中。 二极管形成是通过使用来自P +多晶硅字线的外扩散实现的，其与特定位线区域直接接触。

公开(公告)号：US5643816A

公开(公告)日：1997-07-01

申请号：US454637

申请日：1995-05-31

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L21/265

CPC分类号： H01L27/1021 ,  H01L21/8229 ,  Y10S257/91

摘要： A read-only memory device having a memory array composed of memory cells formed as P-N junction diodes when programmed to be in an ON state and as blocking capacitors when remaining in an OFF state. A number of insulators are placed on the surface of a P-type substrate isolated from each other and aligned along one first defined direction. Each of a number of N-type bit lines is located on the P-type substrate between every neighboring pair of insulators. Each of a number of switch control layers is located on a corresponding one of the N-type bit lines. Each of a number of P-type word lines is located on the insulators along a direction that is substantially perpendicular to the first direction. A punch-through voltage is applied through the switch control layers at selected memory cell locations, thereby programming the memory cell at such locations to be in an ON state. All other memory cells locations keep their switch control layers intact and are thereby programmed to be in an OFF state.

摘要翻译： 具有存储器阵列的只读存储器件，当存储器阵列被编程为处于导通状态时由形成为P-N结二极管的存储器单元组成，并且当保持在断开状态时具有阻塞电容器。 许多绝缘体被放置在彼此隔离并沿着一个第一限定方向对准的P型衬底的表面上。 多个N型位线中的每一个位于每个相邻的绝缘体对之间的P型衬底上。 多个开关控制层中的每一个位于相应的一个N型位线上。 多个P型字线中的每一个沿着基本上垂直于第一方向的方向位于绝缘体上。 通过选择的存储单元位置处的开关控制层施加穿通电压，从而将这样的位置处的存储单元编程为处于导通状态。 所有其他存储单元位置都保持其开关控制层不变，从而被编程为处于OFF状态。

公开(公告)号：US5498556A

公开(公告)日：1996-03-12

申请号：US370617

申请日：1995-01-10

申请人： Gary Hong ,  Chen-Chung Hsu

发明人： Gary Hong ,  Chen-Chung Hsu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/42368 ,  H01L29/6659 ,  H01L29/7834

摘要： The structural configuration of an improved submicron metal-oxide semiconductor field-effect transistor and the method of its fabrication are disclosed. A field oxidation procedure is employed to increase the thickness of the gate oxide layer at both of its ends. The result is decreased gate and drain overlapping region parasitic capacitance, as well as decreased gate-induced drain-leakage current, due to the reduction of the electric field intensity in the overlapping region at which the thickness is increased. The resulting metal-oxide semiconductor field-effect transistor, therefore, is provided with improved operating characteristics for use at high frequencies.

摘要翻译： 公开了改进的亚微米金属氧化物半导体场效应晶体管的结构构造及其制造方法。 采用场氧化工艺来增加其两端的栅极氧化物层的厚度。 由于在厚度增加的重叠区域中的电场强度的降低，结果是栅极和漏极重叠区域寄生电容减小以及栅极引起的漏极 - 漏电流减小。 因此，所得到的金属氧化物半导体场效应晶体管具有在高频下使用的改进的操作特性。

公开(公告)号：US5472897A

公开(公告)日：1995-12-05

申请号：US370611

申请日：1995-01-10

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/66606 ,  H01L29/1083 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/7833

摘要： A method of fabricating MOS device with anti-punchthrough region is described. The area of anti-punchthrough region is reduced by using the control of double spacers. Moreover, this method utilizes the buried contact structure to connect to the source/drain regions, which not only reduces the contact resistance but also reduces the device size since the metal contact can be provided over the field oxide layer instead of the source/drain regions. Hence, this method is capable of fabricating submicron devices for semiconductor integrated circuit.

摘要翻译： 描述了制造具有抗穿通区域的MOS器件的方法。 通过使用双隔板的控制来减少防穿透区域的面积。 此外，该方法利用埋入触点结构连接到源极/漏极区域，这不仅降低了接触电阻，还降低了器件尺寸，因为可以在场氧化物层上提供金属接触而不是源极/漏极区域 。 因此，该方法能够制造用于半导体集成电路的亚微米器件。

公开(公告)号：US5543344A

公开(公告)日：1996-08-06

申请号：US318474

申请日：1994-10-05

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/822 ,  H01L27/10 ,  H01L21/8246

CPC分类号： H01L27/101 ,  H01L21/822 ,  Y10S438/981

摘要： A programmable read-only memory (PROM) and a method of fabrication are described. A plurality of bit-lines of a first conductivity type are formed in a semiconductor substrate and are spaced apart along a first direction. A dielectric layer is disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of vias at predetermined positions above the bit-lines. A plurality of word-lines of a second conductivity type are disposed on the dielectric layer and spaced apart along a second direction substantially orthogonal to the first direction. A control layer is disposed within the vias and sandwiched between the bit-lines and the word-lines, wherein each crossing region of the bit-lines and the word-lines with the control layer disposed there between define a memory cell of the programmable read-only memory. When programming the PROM, selected memory cells of the programmable read-only memory are set in an ON state by applying a programming voltage higher than the normal reading voltage on the word-lines of the selected memory cells while grounding the bit-lines of the selected memory cells to break down the corresponding control layers, whereby the remaining memory cells of the PROM are allowed to remain in an OFF state.

摘要翻译： 描述了可编程只读存储器（PROM）和制造方法。 第一导电类型的多个位线形成在半导体衬底中并且沿着第一方向间隔开。 电介质层设置在半导体衬底上，其中介电层在位线上方的预定位置具有多个通路。 第二导电类型的多个字线布置在电介质层上并且沿着基本上正交于第一方向的第二方向间隔开。 控制层设置在通路内并夹在位线和字线之间，其中位线和字线之间的每个交叉区域与设置在其间的控制层定义可编程读取的存储单元 - 只记忆 当对PROM进行编程时，通过在所选存储单元的字线上施加高于正常读取电压的编程电压，将可编程只读存储器的选定存储单元设置为ON状态，同时将 选择的存储单元来分解对应的控制层，由此允许PROM的剩余存储单元保持在OFF状态。

公开(公告)号：US5453635A

公开(公告)日：1995-09-26

申请号：US358752

申请日：1994-12-19

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L29/66621 ,  Y10S257/90

摘要： A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers to improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

摘要翻译： 描述了轻掺杂漏极（LDD）晶体管器件结构及其制造方法。 提供了在其中形成有沟槽的硅衬底。 在沟槽的侧壁上形成多晶硅侧壁间隔物。 二氧化硅侧壁间隔物形成在多晶硅侧壁间隔物的侧壁上。 通过氧化在沟槽的底部形成栅极氧化层。 形成填充沟槽的多晶硅栅极层。 将杂质注入到硅衬底中，以在邻近多晶硅侧壁间隔物的硅衬底的间隔开的部分中同时形成重掺杂的源极/漏极区，以改善多晶硅栅极层的导电性，并形成间隔开的轻掺杂源极/漏极区 在二氧化硅侧壁间隔下的硅衬底的分开的部分。

公开(公告)号：US6153913A

公开(公告)日：2000-11-28

申请号：US345674

申请日：1999-06-30

申请人： Chen-Chung Hsu ,  Sheng-Hsing Yang

发明人： Chen-Chung Hsu ,  Sheng-Hsing Yang

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L23/60 ,  H01L27/02 ,  H01L23/62

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L23/60 ,  H01L27/0266 ,  H01L2924/0002

摘要： The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region. The silicide blocks are about evenly distributed within the drain region, and preferably distributed in a structure like grid nodes with a shift for the adjacent node row. The silicide includes self-aligned silicide.

摘要翻译： 本发明提供一种形成在半导体衬底上的ESD保护电路。 在I / O端口和内部电路之间的位置处至少有一个MOS晶体管分支出来。 MOS晶体管包括漏极区域，源极区域，栅极氧化物层和栅极电极。 源极和漏极区域形成在衬底中并且位于栅电极的每一侧上。 在衬底上形成绝缘层以覆盖MOS晶体管。 漏极接触形成在绝缘层中，与MOS晶体管的漏极区域接触，使得漏极区域能够通过漏极接触耦合到内部电路。 源极触点形成在绝缘层中，与MOS晶体管的源极区域接触，使得源极区域能够通过源极接触耦合到I / O端口。 几个浮动硅化物块位于漏极区域的绝缘层和衬底之间。 硅化物块大致均匀地分布在漏极区内，并且优选地分布在诸如栅格节点的结构中，具有用于相邻节点行的移位。 硅化物包括自对准硅化物。

公开(公告)号：US6040222A

公开(公告)日：2000-03-21

申请号：US241950

申请日：1999-02-02

申请人： Chen-Chung Hsu ,  Yih-Jau Chang

发明人： Chen-Chung Hsu ,  Yih-Jau Chang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L29/66492 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0266

摘要： An improved method for fabricating an ESD protection device so as to avoid ESD damage to a wafer. The improved method includes simultaneously forming an internal circuit and the ESD protection device without additional photomask or other process. The improved method uses a P.sup.+ doped region to take the place of an N.sup.- doped region of an interchangeable source/drain region with a LDD structure for the ESD protection device, of which its trigger voltage is adjusted by simply varying the P.sup.+ concentration.

摘要翻译： 一种用于制造ESD保护装置以改善对晶片的ESD损伤的改进方法。 改进的方法包括同时形成内部电路和ESD保护装置，而不需要额外的光掩模或其他工艺。 改进的方法使用P +掺杂区域代替具有用于ESD保护器件的LDD结构的可互换源极/漏极区域的N-掺杂区域，其触发电压通过简单地改变P +浓度来调节。