公开(公告)号：US20090024786A1

公开(公告)日：2009-01-22

申请号：US11875964

申请日：2007-10-22

申请人： Cheng-Sheng Chan ,  Chih-Chin Yang ,  Chia-Chang Lee

发明人： Cheng-Sheng Chan ,  Chih-Chin Yang ,  Chia-Chang Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/0866 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F2212/222

摘要： An external storage device includes a hard-drive, a flash memory, and a memory arrangement unit. The memory arrangement determines if the tag of the data accessed by a computer stored in the tag list of the memory arrangement unit and controls the hard-drive and the flash memory according to the result of the determination.

摘要翻译： 外部存储装置包括硬盘驱动器，闪速存储器和存储器布置单元。 存储器装置确定由存储在存储器配置单元的标签列表中的计算机访问的数据的标签是否根据确定的结果来控制硬盘驱动器和闪速存储器。

公开(公告)号：US5870625A

公开(公告)日：1999-02-09

申请号：US570441

申请日：1995-12-11

申请人： Cheng-Sheng Chan ,  Tienyo Pan

发明人： Cheng-Sheng Chan ,  Tienyo Pan

IPC分类号： G06F9/38 ,  G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/3824

摘要： A computer system is disclosed which has a plurality of masters, such as a processor, a cache memory or an I/O device controller. Read response time from the main memory is minimized by a read-from-write scheme which gives priority to read commands. If a read command is to access data with the same address of a previously issued but pending write command in the buffer of a memory controller, then the read and write commands are combined and the read/write command is given priority over each other pending read or write command. To further reduce mean read response time, the data to be written to the main memory is transferred directly from the buffer to the master which issued the read command contemporaneously with the execution of the write command on the main memory.

摘要翻译： 公开了一种计算机系统，其具有多个主器件，诸如处理器，高速缓冲存储器或I / O设备控制器。 通过读写方式将从主存储器读取的响应时间最小化，优先读取命令。 如果读取命令要访问具有与存储器控制器的缓冲器中的先前发布但尚待写入的命令相同的地址的数据，则读取和写入命令被组合，并且读取/写入命令被优先于彼此等待读取 或写命令。 为了进一步减小平均读取响应时间，将要写入主存储器的数据直接从缓冲器传送到与主存储器上执行写入命令同时发出读取命令的主器件。

公开(公告)号：US20070150781A1

公开(公告)日：2007-06-28

申请号：US11640863

申请日：2006-12-19

申请人： Po-Yuan Chen ,  Cheng-Sheng Chan ,  Hui-Ming Lin

发明人： Po-Yuan Chen ,  Cheng-Sheng Chan ,  Hui-Ming Lin

IPC分类号： G01R31/28

CPC分类号： G01R31/318516 ,  G01R31/318536 ,  G01R31/318541

摘要： An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one of the plurality of first I/O ports to be coupled to the scan input port, a plurality of second I/O ports, an output port selector for selecting one of the plurality of second I/O ports to be coupled to said scan output port. Further, an apparatus provided with programmable scan chains includes N scan chains, each scan chain having a scan input port and scan output port, M first I/O ports, an input port selector for selecting N of the first I/O ports to be coupled to the N scan input ports, K second I/O ports, and an output port selector for selecting N of the second I/O ports to be coupled to the N scan output ports.

摘要翻译： 提供有可编程扫描链的装置包括具有扫描输入端口和扫描输出端口的扫描链，多个第一I / O端口，用于选择要耦合的多个第一I / O端口之一的输入端口选择器 到扫描输入端口，多个第二I / O端口，用于选择要耦合到所述扫描输出端口的多个第二I / O端口中的一个的输出端口选择器。 另外，设置有可编程扫描链的装置包括N个扫描链，每个扫描链具有扫描输入端口和扫描输出端口，M个第一I / O端口，用于选择N个第一I / O端口的输入端口选择器 耦合到N个扫描输入端口，K个第二I / O端口，以及输出端口选择器，用于选择N个与N个扫描输出端口耦合的第二I / O端口。

公开(公告)号：US5822772A

公开(公告)日：1998-10-13

申请号：US620592

申请日：1996-03-22

申请人： Cheng-Sheng Chan ,  Tienyo Pan

发明人： Cheng-Sheng Chan ,  Tienyo Pan

IPC分类号： G11C7/22 ,  G06F13/18 ,  G06F12/00

CPC分类号： G11C7/22

摘要： An improved memory controller is disclosed for accessing a computer memory, which consists of a plurality of banks of page mode memory cells and is connected to a CPU via a split transaction bus with out-of-order completion capability. The improved memory controller comprises: (a) a unified command queue for receiving a memory access command; (b) a plurality of command queues equalling in number to the number of the memory banks; (c) a dispatch logic for dispatching the memory access command into one of the command queues in accordance with which memory bank the access command is to access; (d) a selection logic for selecting one of the command queues as an active command queue to execute a command, wherein all the non-selected command queues are placed on a standby status as standby command queues; and (e) switching logic provided in the selection logic for switching the command execution from the active command queue to a standby command queue, which is made active according to a predetermined criterion, when a page miss is detected or when the active command queue is empty. The switching logic also causes one of the standby command queues to perform a row address selection when the active command queue is accessing said computer memory. With the improved memory controller, penalties associated with row miss and/or page miss are eliminated. As a result, the average memory access latency is minimized and overall memory utilization efficiency is enhanced.

摘要翻译： 公开了一种改进的存储器控​​制器，用于访问由多个页模式存储单元组组成的计算机存储器，并且经由具有无序完成能力的分割事务总线连接到CPU。 改进的存储器控​​制器包括：（a）用于接收存储器访问命令的统一命令队列; （b）多个与存储体的数量相等的命令队列; （c）调度逻辑，用于根据访问命令要访问的存储器组，将存储器访问命令分派到一个命令队列中; （d）用于选择一个命令队列作为活动命令队列以执行命令的选择逻辑，其中所有未选择的命令队列作为备用命令队列置于备用状态; 以及（e）提供在选择逻辑中的切换逻辑，用于将命令执行从活动命令队列切换到备用命令队列，当检测到页面未命中时，或当活动命令队列为 空的 当活动命令队列正在访问所述计算机存储器时，切换逻辑还使其中一个备用命令队列执行行地址选择。 利用改进的存储器控​​制器，消除了与行缺失和/或页错误相关联的惩罚。 结果，平均存储器访问延迟最小化并且总体存储器利用效率增强。

公开(公告)号：US08209452B2

公开(公告)日：2012-06-26

申请号：US12365175

申请日：2009-02-04

申请人： Liang-Chun Lin ,  Cheng-Sheng Chan

发明人： Liang-Chun Lin ,  Cheng-Sheng Chan

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F12/00 ,  G06F21/00 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F13/4027 ,  G06F13/105

摘要： An external device includes a bridge and a storage device. The bridge is connected to a host according to a first data transmission interface so as to convert data of the host from the first data transmission interface to a second data transmission interface. The bridge includes a memory unit and a control unit. The memory unit stores a virtual device datum. The control unit generates a virtual storage device in the host according to the virtual device datum. The storage device is connected to the bridge for storing the data of the host according to the second data transmission interface.

摘要翻译： 外部设备包括桥接器和存储设备。 桥接器根据第一数据传输接口连接到主机，以将主机的数据从第一数据传输接口转换为第二数据传输接口。 该桥包括一个存储单元和一个控制单元。 存储器单元存储虚拟设备基准。 控制单元根据虚拟设备数据在主机中生成虚拟存储设备。 存储装置连接到桥接器，用于根据第二数据传输接口存储主机的数据。

公开(公告)号：US20100180080A1

公开(公告)日：2010-07-15

申请号：US12466389

申请日：2009-05-15

申请人： Liang-Chun Lin ,  Cheng-Sheng Chan

发明人： Liang-Chun Lin ,  Cheng-Sheng Chan

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F12/1458

摘要： An external storage device includes a storage device and a bridge. The storage device stores data transmitted from a computer host. The bridge includes a memory unit and a control unit. The memory unit stores a virtual device datum, and the virtual device datum includes an application program. The control unit generates a virtual storage device in the computer host according to the virtual device datum, and executes a security function of the storage device according to the application program.

摘要翻译： 外部存储装置包括存储装置和桥。 存储设备存储从计算机主机发送的数据。 该桥包括一个存储单元和一个控制单元。 存储单元存储虚拟设备数据，并且虚拟设备数据包括应用程序。 控制单元根据虚拟设备数据在计算机主机中生成虚拟存储装置，根据应用程序执行存储装置的安全功能。

公开(公告)号：US07600168B2

公开(公告)日：2009-10-06

申请号：US11640863

申请日：2006-12-19

申请人： Po-Yuan Chen ,  Cheng-Sheng Chan ,  Hui-Ming Lin

发明人： Po-Yuan Chen ,  Cheng-Sheng Chan ,  Hui-Ming Lin

IPC分类号： G01R31/28

CPC分类号： G01R31/318516 ,  G01R31/318536 ,  G01R31/318541

摘要： An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one of the plurality of first I/O ports to be coupled to the scan input port, a plurality of second I/O ports, an output port selector for selecting one of the plurality of second I/O ports to be coupled to said scan output port. Further, an apparatus provided with programmable scan chains includes N scan chains, each scan chain having a scan input port and scan output port, M first I/O ports, an input port selector for selecting N of the first I/O ports to be coupled to the N scan input ports, K second I/O ports, and an output port selector for selecting N of the second I/O ports to be coupled to the N scan output ports.

摘要翻译： 提供有可编程扫描链的装置包括具有扫描输入端口和扫描输出端口的扫描链，多个第一I / O端口，用于选择要耦合的多个第一I / O端口之一的输入端口选择器 到扫描输入端口，多个第二I / O端口，用于选择要耦合到所述扫描输出端口的多个第二I / O端口中的一个的输出端口选择器。 另外，设置有可编程扫描链的装置包括N个扫描链，每个扫描链具有扫描输入端口和扫描输出端口，M个第一I / O端口，用于选择N个第一I / O端口的输入端口选择器 耦合到N个扫描输入端口，K个第二I / O端口，以及输出端口选择器，用于选择N个与N个扫描输出端口耦合的第二I / O端口。

公开(公告)号：US5940870A

公开(公告)日：1999-08-17

申请号：US651150

申请日：1996-05-21

申请人： Hsin-Chou Chi ,  Yeong-Chang Maa ,  Cheng-Sheng Chan

发明人： Hsin-Chou Chi ,  Yeong-Chang Maa ,  Cheng-Sheng Chan

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F9/06

CPC分类号： G06F12/0692 ,  G06F12/0813 ,  G06F2212/2542

摘要： An address translation method for use in a system including a plurality of cluster nodes and including the steps of: at a source node, receiving over a first network a communication with a first destination address having an index portion and an offset portion, wherein the index portion includes a partition number portion; providing an address mapping table which maps a plurality of indexes to a corresponding plurality of node ID's, each of the plurality of node ID's identifying a different one of the plurality of cluster nodes; using the index portion from the first destination address as an index into the address mapping table to identify a node ID, wherein the identified node ID identifies a destination node; appending the identified node ID to the first destination address to generate a second destination address; and using the second destination address to send information to a second network of the destination node.

摘要翻译： 一种在包括多个集群节点的系统中使用的地址转换方法，包括以下步骤：在源节点处，通过第一网络接收与具有索引部分和偏移部分的第一目的地地址的通信，其中所述索引 部分包括分区号部分; 提供将多个索引映射到对应的多个节点ID的地址映射表，所述多个节点ID中的每一个识别所述多​​个集群节点中的不同的一个; 使用来自第一目的地地址的索引部分作为地址映射表的索引，以标识节点ID，其中所标识的节点ID标识目的地节点; 将所识别的节点ID附加到第一目的地地址以生成第二目的地地址; 以及使用所述第二目的地地址将信息发送到所述目的地节点的第二网络。

公开(公告)号：US20100125688A1

公开(公告)日：2010-05-20

申请号：US12365175

申请日：2009-02-04

申请人： Liang-Chun Lin ,  Cheng-Sheng Chan

发明人： Liang-Chun Lin ,  Cheng-Sheng Chan

IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F3/00

CPC分类号： G06F13/4027 ,  G06F13/105

摘要： An external device includes a bridge and a storage device. The bridge is connected to a host according to a first data transmission interface so as to convert data of the host from the first data transmission interface to a second data transmission interface. The bridge includes a memory unit and a control unit. The memory unit stores a virtual device datum. The control unit generates a virtual storage device in the host according to the virtual device datum. The storage device is connected to the bridge for storing the data of the host according to the second data transmission interface.

摘要翻译： 外部设备包括桥接器和存储设备。 桥接器根据第一数据传输接口连接到主机，以将主机的数据从第一数据传输接口转换为第二数据传输接口。 该桥包括一个存储单元和一个控制单元。 存储器单元存储虚拟设备基准。 控制单元根据虚拟设备数据在主机中生成虚拟存储设备。 存储装置连接到桥接器，用于根据第二数据传输接口存储主机的数据。