公开(公告)号：US07099539B1

公开(公告)日：2006-08-29

申请号：US10615318

申请日：2003-07-07

申请人： Chi Au ,  Tzu-Yih Chu ,  Hao Yin ,  Abraham C. Ma ,  Edward W. Lee

发明人： Chi Au ,  Tzu-Yih Chu ,  Hao Yin ,  Abraham C. Ma ,  Edward W. Lee

IPC分类号： G02B6/26

CPC分类号： G02B6/2746 ,  G02B6/125 ,  G02B6/266

摘要： An optical system and associated method are provided. Included is a first branch capable of allowing light to pass therethrough in a forward direction and a reverse direction. The first branch includes a first medium with a first refractive index (n1), and a first end and a second end. Also included is a second branch capable of allowing light to pass therethrough in the forward direction. The second branch includes a second medium with a second refractive index (n2, with n2

摘要翻译： 提供了一种光学系统及相关方法。 包括能够使光从正向和反方向通过的第一分支。 第一分支包括具有第一折射率（n <1> 1）的第一介质，以及第一端和第二端。 还包括能够允许光沿正向通过的第二分支。 第二分支包括第二介质，其具有第二折射率（n _{2，n≥2 <= SIN＆lt; 1＆gt;（n2 / n＆lt; 1＆gt; 通过第一分支的光通过第二分支，其中θ1是从第一分支到第二分支的反向通过的光的入射角。}

公开(公告)号：US06522462B2

公开(公告)日：2003-02-18

申请号：US09682283

申请日：2001-08-14

申请人： Tzu-Yih Chu ,  Shyang Chang ,  Chi Au ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Shyang Chang ,  Chi Au ,  Abraham C. Ma

IPC分类号： H01S300

CPC分类号： G02F2/004 ,  G02B6/26 ,  G02B6/29352 ,  G02F3/00 ,  G02F2203/70

摘要： Optical logic gates are constructed from Mach-Zehnder Interferometer (MZI) optical circuits. A multi-mode interference (MMI) splitter divides a continuous-wave input into two branches of the interferometer. Each branch has a semiconductor optical amplifier (SOA). When a logic input having a logic-high power level is applied to one of the SOA's, cross-phase modulation occurs in the SOA. The phase shift increases through the SOA. The branch coupled to the logic input has a relative phase shift of &pgr; compared with the other branch. When two branches with the &pgr; phase difference are combined, destructive interference occurs, producing a logic low. An MMI combiner or an equivalent phase shifter is used to combine the two branches. The MMI splitter adds a phase shift of &pgr;/2 to the upper branch but not to the lower branch, while the MMI combiner also adds &pgr;/2 shifts.

摘要翻译： 光逻辑门由Mach-Zehnder干涉仪（MZI）光电路构成。 多模干扰（MMI）分离器将连续波输入分成干涉仪的两个分支。 每个分支都有一个半导体光放大器（SOA）。 当具有逻辑高功率电平的逻辑输入被应用于SOA中的一个时，在SOA中发生交叉相位调制。 相移通过SOA增加。 耦合到逻辑输入的分支与其他分支相比具有pi的相对相移。 当具有pi相位差的两个分支组合时，发生相消干扰，产生逻辑低电平。 使用MMI组合器或等效移相器来组合两个分支。 MMI分路器将pi / 2的相移添加到上分支，但不分配给下分支，而MMI组合器也增加pi / 2移位。

公开(公告)号：US06462865B1

公开(公告)日：2002-10-08

申请号：US09681964

申请日：2001-06-29

申请人： Tzu-Yih Chu ,  Shyang Chang ,  Chi Au ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Shyang Chang ,  Chi Au ,  Abraham C. Ma

IPC分类号： H01S300

CPC分类号： H01S5/50 ,  G02F2/004 ,  G02F3/00 ,  G02F2203/70

摘要： A novel semiconductor optical amplifier (SOA) can operate as an optical inverter as well as a power-restoring device. Together, an optical-OR and the optical inverter can provide a wide variety of high speed optical logic gates and functions. The optical inverter uses cross-gain modulation (XGM) to invert a modulated signal on a first input, to produce an inverted output. The inverse of the modulation is transferred from a first wavelength of the modulated first input to a second wavelength of a continuous-wave second input. A filter can then block the first wavelength, allowing the inversely-modulated second wavelength to be output as the inverted output. The first and second wavelengths are swapped in alternate inverters in a logic path. The Y-junction can be implemented as a Multi-Mode Interference (MMI) device.

摘要翻译： 一种新型的半导体光放大器（SOA）可以作为光逆变器以及功率恢复装置。 光学和光学逆变器一起可以提供各种各样的高速光逻辑门和功能。 光反向器使用交叉增益调制（XGM）来反转第一输入上的调制信号，以产生反相输出。 调制的反相从调制的第一输入的第一波长传送到连续波第二输入的第二波长。 滤波器然后可以阻挡第一波长，允许反向调制的第二波长作为反相输出输出。 第一和第二波长交替在逻辑路径中的交替逆变器中。 Y结可以实现为多模干扰（MMI）设备。

公开(公告)号：US5941447A

公开(公告)日：1999-08-24

申请号：US162430

申请日：1998-09-28

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  B23K31/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost. The capacitors are mounted on the opposite surface from the large processor for efficiency.

摘要翻译： 处理器模块具有安装在背面和前表面上的SRAM芯片的高速缓存，但是只耦合安装在背面上的电容器。 每个去耦电容器用于抑制来自一对SRAM芯片的电流尖峰。 这对SRAM芯片包括与电容器相同表面上的第一SRAM芯片和与模块前表面上的第一SRAM芯片相对的第二SRAM芯片。 第一个SRAM芯片属于第一个bank，而第二个SRAM芯片属于第二个bank。 两个芯片使能信号控制对两个存储体的访问。 由于在任何时间只访问一个存储区，访问引起电流尖峰，所以SRAM对中的只有一个存储体和只有一个SRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个SRAM芯片之间共享电容器。 共享电容器可以安装在SRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。 电容器安装在与大型处理器相反的表面上，以提高效率。

公开(公告)号：US05996880A

公开(公告)日：1999-12-07

申请号：US56152

申请日：1998-04-06

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  B23K31/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost.

摘要翻译： 存储器模块具有安装在前表面和后表面上的DRAM芯片，但是仅去除仅安装在前表面上的电容器。 每个去耦电容器用于抑制来自一对DRAM芯片的电流尖峰。 一对DRAM芯片包括与电容器相同的表面上的第一DRAM芯片和与模块背面上的第一DRAM芯片相对的第二DRAM芯片。 第一DRAM芯片属于第一存储体，而第二DRAM芯片属于第二存储体。 两个RAS信号用于控制对两个银行的访问。 由于在任何时间只访问一个存储体，访问引起电流尖峰，所以DRAM芯片对中只有一个存储体和只有一个DRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个DRAM芯片之间共享电容器。 共享电容器可以安装在DRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。

公开(公告)号：US5856937A

公开(公告)日：1999-01-05

申请号：US876135

申请日：1997-06-23

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  G11C5/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost. The capacitors are mounted on the opposite surface from the large processor for efficiency.

摘要翻译： 处理器模块具有安装在背面和前表面上的SRAM芯片的高速缓存，但是只耦合安装在背面上的电容器。 每个去耦电容器用于抑制来自一对SRAM芯片的电流尖峰。 这对SRAM芯片包括与电容器相同表面上的第一SRAM芯片和与模块前表面上的第一SRAM芯片相对的第二SRAM芯片。 第一个SRAM芯片属于第一个bank，而第二个SRAM芯片属于第二个bank。 两个芯片使能信号控制对两个存储体的访问。 由于在任何时间只访问一个存储区，访问引起电流尖峰，所以SRAM对中的只有一个存储体和只有一个SRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个SRAM芯片之间共享电容器。 共享电容器可以安装在SRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。 电容器安装在与大型处理器相反的表面上，以提高效率。

公开(公告)号：US06542671B1

公开(公告)日：2003-04-01

申请号：US09683306

申请日：2001-12-12

申请人： Abraham C. Ma ,  Tzu-Yih Chu

发明人： Abraham C. Ma ,  Tzu-Yih Chu

IPC分类号： G02B626

CPC分类号： G02B6/12007 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/29361 ,  G02B6/29364 ,  G02B2006/12109

摘要： An integrated optical device has two waveguide layers that are patterned to provide 2-dimensional interconnected networks of waveguides. A filter layer between the two waveguide layers is made by sputter deposition of thin films with alternating indexes of refraction. Light traveling vertically through the filter layer experiences an interferometric effect. A deflecting bump is formed in the plane of the lower waveguide layer. The bump is isotropicly etched, undercutting a photo-mask over the bump, producing a rounded, concave profile to the bump. High-index material is deposited over the bump and patterned to form a waveguide that has light deflected by the bump upward. The filter is formed over the bump to receive the deflected light. The filter reflects some light back down to the bump to another waveguide in the first layer. Light transmitted vertically up through the filter is bent to the horizontal plane of the upper waveguide layer.

摘要翻译： 集成光学器件具有被图案化以提供二维互连的波导网络的两个波导层。 通过溅射沉积具有交替的折射率的薄膜来制造两个波导层之间的滤光层。 通过过滤层垂直行进的光线经历干涉效应。 在下波导层的平面中形成偏转凸块。 凸块被各向同性地蚀刻，在凸块上切割光掩模，产生凹凸的圆形凹形轮廓。 高折射率材料沉积在凸块上并被图案化以形成具有由凸起向上偏转的光的波导。 过滤器形成在凸起上以接收偏转的光。 滤光器将一些光反射回第一层中另一个波导的凸起。 通过滤光器垂直向上透射的光被弯曲到上波导层的水平面。

公开(公告)号：US5841686A

公开(公告)日：1998-11-24

申请号：US755546

申请日：1996-11-22

申请人： Tzu-Yih Chu ,  Abraham C. Ma

发明人： Tzu-Yih Chu ,  Abraham C. Ma

IPC分类号： G11C5/00 ,  G11C8/12 ,  H05K1/02 ,  H05K1/16 ,  G11C5/02

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C8/12 ,  H05K1/0231 ,  H05K1/023 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10689

摘要： A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost.

摘要翻译： 存储器模块具有安装在前表面和后表面上的DRAM芯片，但是仅去除仅安装在前表面上的电容器。 每个去耦电容器用于抑制来自一对DRAM芯片的电流尖峰。 一对DRAM芯片包括与电容器相同的表面上的第一DRAM芯片和与模块背面上的第一DRAM芯片相对的第二DRAM芯片。 第一DRAM芯片属于第一存储体，而第二DRAM芯片属于第二存储体。 两个RAS信号用于控制对两个银行的访问。 由于在任何时间只访问一个存储体，访问引起电流尖峰，所以DRAM芯片对中只有一个存储体和只有一个DRAM芯片可以随时创建电流尖峰。 因此，可以在该对中的两个DRAM芯片之间共享电容器。 共享电容器可以安装在DRAM芯片旁边或下面，或者形成在多层基板本身内。 仅在其中一个表面上放置电容器可减少所需的放置顺序数量，从而降低制造成本。

公开(公告)号：US07004794B2

公开(公告)日：2006-02-28

申请号：US10917672

申请日：2004-08-13

申请人： Kuang-Yu Wang ,  Jim Ni ,  Ren-Kang Chiou ,  Edward W. Lee ,  Tzu-Yih Chu

发明人： Kuang-Yu Wang ,  Jim Ni ,  Ren-Kang Chiou ,  Edward W. Lee ,  Tzu-Yih Chu

IPC分类号： H01R33/00

CPC分类号： G06K19/07732 ,  G06K19/07733 ,  H01R24/62

摘要： A low-profile Universal-Serial-Bus (USB) connector includes a substantially flat base structure that is received in the lower section of a conventional female USB connector, and includes metal contacts formed on an upper surface of the base structure. Wobble or vertical play is reduced by rails extending along side edges of the base structure that are partially inserted into gaps formed between the metal case and base structure of the female USB connector. Between metal contacts on the low-profile USB connector are raised ribs (dividers) that prevent undesirable damage or contamination to the metal contacts. The connector base structure of the low-profile USB connector can be separate or can be integrated with a circuit board that holds a flash memory chip and a USB controller chip.

摘要翻译： 一种低调的通用串行总线（USB）连接器包括基本上平坦的基座结构，其被接收在传统的母USB连接器的下部，并且包括形成在基座结构的上表面上的金属触点。 摇摆或垂直播放通过沿底座结构的侧边缘延伸的轨道减少，该轨道部分地插入形成在母壳式USB连接器的金属外壳和基座结构之间的间隙中。 在薄型USB连接器上的金属触点之间是凸肋（分隔线），可防止不必要的金属触点损坏或污染。 低调USB连接器的连接器基座结构可以是独立的，也可以与保存闪存芯片和USB控制器芯片的电路板集成。

公开(公告)号：USRE40115E1

公开(公告)日：2008-02-26

申请号：US11106735

申请日：2005-04-13

申请人： Edward W. Lee ,  Ren-Kang Chiou ,  Tzu-Yih Chu

发明人： Edward W. Lee ,  Ren-Kang Chiou ,  Tzu-Yih Chu

IPC分类号： H01R12/00

CPC分类号： G06K19/07732 ,  G06K19/07733 ,  H01R24/62 ,  H01R27/02

摘要： A slim male Universal-Serial-Bus (USB) connector fits on only one side of the connector substrate in a standard female USB connector. Wobble or vertical play is reduced by locking depressions in the slim male USB connector that engage metal springs on a metal case that surrounds the female USB connector, locking the two connectors together. Between metal contacts on the slim USM connector are dividers that help fill in gaps when the two connectors are connected together, further reducing play. End rails on the slim USB connector fill in gaps on the sides. The connector substrate of the slim male USB connector can be separate or can be integrated with a circuit board that holds a flash memory chip and a USB controller chip. The connector is wider than the standard width for a better fit. A slim female USB connector for assembly use with the slim male USB connector is also disclosed.

摘要翻译： 通用串行总线（USB）连接器适合于通用串行总线（USB）连接器，适用于<？insert-start id =“INS-S-00001”date =“20080226”？> male <？insert-end id =“INS-S-00001”？ 仅在标准母USB连接器中的连接器基板的一侧。 摆动或垂直播放通过在细长状态下锁定凹陷来减少<？insert-start id =“INS-S-00002”date =“20080226”？> male <？insert-end id =“INS-S-00002”？> USB连接器，将金属弹簧接合在围绕母USB连接器的金属外壳上，将两个连接器锁定在一起。 在超薄USM连接器上的金属触点之间的分隔线有助于在两个连接器连接在一起时填补间隙，进一步减少播放。 超薄USB连接器上的端部导轨填充两侧的间隙。 USB连接器的连接器基板可以是单独的或者是可以分开的，这个连接器基板的尺寸<？insert-start id =“INS-S-00003”date =“20080226”？> male <？insert-end id =“INS-S-00003” 可以与保存闪存芯片和USB控制器芯片的电路板集成。 连接器比标准宽度更宽，更好的适合。 一个细长的母USB连接器，用于组装<？insert-start id =“INS-S-00004”date =“20080226”？>使用细长的公头USB？<？insert-end id =“INS-S-00004”？ 连接器也被公开。