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    Master image chip organization technique or method
    5.
    发明授权
    Master image chip organization technique or method 失效
    主图像芯片组织技术或方法

    公开(公告)号：UST106201I4

    公开(公告)日：1986-03-04

    申请号：US457786

    申请日：1983-01-13

    申请人： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

    发明人： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

    IPC分类号： H01L23/528 ,  H01L27/118

    CPC分类号： H01L23/528 ,  H01L27/11801 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern of conductors, and each of said connections occurring exclusively at points in space corresponding to X-Y intersections of an X-Y coordinate system, where said X-Y coordinate system geometrically corresponds identically to said X-Y pattern of conductors.

    Master image chip organization technique or method
    6.
    发明授权
    Master image chip organization technique or method 失效
    主图像芯片组织技术或方法

    公开(公告)号：US4295149A

    公开(公告)日：1981-10-13

    申请号：US974576

    申请日：1978-12-29

    申请人： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

    发明人： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

    CPC分类号： H01L27/11801 ,  H01L23/528 ,  H01L2924/0002

    摘要： Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions.In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

    摘要翻译： 公开了被称为“主映像芯片组织技术”的改进的LSI半导体设计结构。 利用该技术提供了增加的密度和优化的半导体器件，电路和部件号功能的性能。 根据所公开的主图像芯片组合方法，半导体芯片被最佳地构造以便于最大数量的器件和电路，并且有助于制造各种LSI部件号。 基本上，半导体表面都没有专用于信号和电源布线通道。 提供了主图像布线结构，其驻留在半导体表面上并在功率表面下方。 此外，主图像布线结构提供了用于个性化用于多功率表面结构的功率和信号布线的装置。 组合的主图像结构提供了用于最佳地分配设备，功能单元（微和宏）以及信号和电力布线的半导体区域以便于改进密度和性能的手段。

    LSI Semiconductor device and fabrication thereof
    7.
    发明授权
    LSI Semiconductor device and fabrication thereof 失效
    LSI半导体器件及其制造

    公开(公告)号：US4249193A

    公开(公告)日：1981-02-03

    申请号：US909605

    申请日：1978-05-25

    申请人： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

    发明人： John Balyoz ,  Chi S. Chang ,  Barry C. Fox ,  John A. Palmieri ,  Majid Ghafghaichi ,  Teh-Sen Jen ,  Donald B. Mooney

    IPC分类号： H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/02

    CPC分类号： H01L23/528 ,  H01L27/11801 ,  H01L2924/0002 ,  Y10S257/923

    摘要： Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices.In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

    摘要翻译： 公开了一种改进的主机设计技术，包括结构，布线和制造方法，以提供改进的大规模集成器件。 根据改进的主机技术，提供了多个半导体芯片，其中基本上每个芯片的整个半导体表面积用于提供可选择的个性化（有线）的单元。 半导体表面积都不用于布线通道。 如果不是全部包含在每个芯片上的单元，则可以最佳地达到单个单元面积和单元配置以便最大数量的布线，从而可以容易地制造各种LSI器件部件号，从而电路密度得到实质性改善。