公开(公告)号：US20230217600A1

公开(公告)日：2023-07-06

申请号：US17689986

申请日：2022-03-09

申请人： HERMES TESTING SOLUTIONS INC.

发明人： Chiao-Pei Chen ,  Chun-Hsiung Chou

IPC分类号： H05K3/46 ,  H05K1/02 ,  G01R1/073

CPC分类号： H05K3/462 ,  H05K1/0284 ,  G01R1/07307 ,  H05K2203/016

摘要： A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.

公开(公告)号：US20190008044A1

公开(公告)日：2019-01-03

申请号：US15635201

申请日：2017-06-28

申请人： Sierra Circuits, Inc.

发明人： Konstantine KARAVAKIS ,  Kenneth S. BAHL

IPC分类号： H05K1/11 ,  H05K3/46 ,  H05K3/18 ,  H05K3/06 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K1/0313 ,  H05K1/095 ,  H05K1/111 ,  H05K3/06 ,  H05K3/181 ,  H05K3/425 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/068 ,  H05K2203/085

摘要： A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

公开(公告)号：US20180146554A1

公开(公告)日：2018-05-24

申请号：US15819133

申请日：2017-11-21

申请人： IBIDEN CO., LTD.

发明人： Kazuki Kajihara ,  Naoki Kurahashi

IPC分类号： H05K1/14 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K3/40 ,  H05K3/46

CPC分类号： H05K1/144 ,  H01L21/4857 ,  H01L23/49822 ,  H05K1/0243 ,  H05K1/028 ,  H05K1/111 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4007 ,  H05K3/462 ,  H05K3/4638 ,  H05K3/4697 ,  H05K2201/09063 ,  H05K2201/096 ,  H05K2203/166

摘要： A wiring substrate includes a first substrate including a first conductive circuit layer, a second substrate including a second conductive circuit layer, and a substrate fixing structure fixing the first substrate and the second substrate to each other such that the first substrate and the second substrate are superposed on each other. The first conductive layer in the first substrate includes a first counter electrode, the second conductive layer in the second substrate includes a second counter electrode, and the first and second substrates have a hollow space formed such that the first and second counter electrodes are positioned to oppose each other across the hollow space and that the first and second substrates have a dividing plane intersecting the hollow space and dividing the first and second substrates.

公开(公告)号：US09437489B2

公开(公告)日：2016-09-06

申请号：US14095182

申请日：2013-12-03

申请人： Seiko Epson Corporation

发明人： Tsuyoshi Yoda

IPC分类号： H01L21/768 ,  H05K3/40 ,  H05K3/22 ,  H05K3/32 ,  H05K3/42 ,  H05K3/46 ,  B81B7/00 ,  G01C19/56 ,  G01C19/5776 ,  H01L23/48

CPC分类号： H01L21/76898 ,  B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0271 ,  G01C19/56 ,  G01C19/5776 ,  H01L21/76877 ,  H01L23/481 ,  H01L2924/00 ,  H01L2924/0002 ,  H05K3/225 ,  H05K3/321 ,  H05K3/4038 ,  H05K3/429 ,  H05K3/462 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49139

摘要： A method of manufacturing a wiring substrate including a step of forming a through hole that includes forming a first concave portion in a substrate that extends from a second surface to a first insulating layer without passing through the first insulating layer; forming a second insulating layer at least within the first concave portion; and forming a second concave portion through the second insulating layer and the first insulating layer to expose a surface of a pad electrode, wherein the second concave portion is formed within the first concave portion; and filling the first concave portion and the second concave portion with a conductive body or forming the conductive body to coat inner walls of the first concave portion and the second concave portion, and forming the through electrode such that it is connected to the pad electrode.

摘要翻译： 一种制造布线基板的方法，包括形成通孔的步骤，所述通孔包括在不通过所述第一绝缘层的情况下从第二表面延伸到第一绝缘层的基板中形成第一凹部; 至少在所述第一凹部内形成第二绝缘层; 以及通过所述第二绝缘层和所述第一绝缘层形成第二凹部以暴露焊盘电极的表面，其中所述第二凹部形成在所述第一凹部内; 并且用导电体填充第一凹部和第二凹部，或者形成导电体以涂覆第一凹部和第二凹部的内壁，并且形成贯通电极，使其与焊盘电极连接。

公开(公告)号：US20160247753A1

公开(公告)日：2016-08-25

申请号：US15048250

申请日：2016-02-19

申请人： KYOCERA Circuit Solutions, Inc.

发明人： Keizou SAKURAI

IPC分类号： H01L23/498 ,  H05K1/02 ,  H05K3/00 ,  H01L21/48

CPC分类号： H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5389 ,  H05K1/0298 ,  H05K3/0058 ,  H05K3/462 ,  H05K3/4697

摘要： A method of manufacturing a cavity substrate of the present invention includes respectively laminating second and third substrates on upper and lower surfaces of a first substrate having an opening and having an external dimension larger than an external dimension of each of the second and third substrates to ensure that an end portion of the first substrate protrudes a first length from the second and third substrates, and cutting the end portion of the first substrate protruding from each of the second and third substrates to a second length smaller than the first length.

摘要翻译： 本发明的空心衬底的制造方法包括在具有开口的第一衬底的上表面和下表面上分别层叠第二和第三衬底，并且具有大于第二和第三衬底中的每一个的外部尺寸的外部尺寸，以确保 第一基板的端部从第二和第三基板突出第一长度，并且将从第二和第三基板中的每一个突出的第一基板的端部切割成小于第一长度的第二长度。

公开(公告)号：US09357640B2

公开(公告)日：2016-05-31

申请号：US14853125

申请日：2015-09-14

申请人： Océ-Technologies B.V.

发明人： Hendrikus J. T. M. Van den Bersselaar

IPC分类号： H05K3/00 ,  H05K1/03 ,  H05K3/46 ,  H05K3/06 ,  H05K1/02 ,  H05K3/38

CPC分类号： H05K1/03 ,  H05K1/0298 ,  H05K3/0085 ,  H05K3/061 ,  H05K3/38 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2203/013

摘要： A method of manufacturing a multi-layer printed circuit board by bonding together a plurality of circuit board layers, each of which includes a substrate and a conductive circuit pattern on at least one surface of the substrate, includes the steps of: coating the surface of the substrate with a continuous layer of conductive material, masking the layer with a resist, etching away a part of the conductive material so as to obtain the circuit pattern with conductive parts separated by gaps, and filling the gaps with an electrically insulating adhesive material to a level that is at least equal to the thickness of the layer of conductive material. The resist is left on the conductive parts and the adhesive material is selected to be chemically compatible with the resist.

摘要翻译： 一种多层印刷电路板的制造方法，其特征在于，在所述基板的至少一个表面上包含基板和导电电路图案的多个电路基板层粘合在一起，其特征在于，包括： 具有连续导电材料层的衬底，用抗蚀剂掩蔽该层，蚀刻掉导电材料的一部分，以获得具有由间隙分离的导电部件的电路图案，并用电绝缘粘合剂材料填充间隙 至少等于导电材料层的厚度的水平。 抗蚀剂留在导电部分上，并且粘合剂材料被选择为与抗蚀剂化学相容。

公开(公告)号：US20150382459A1

公开(公告)日：2015-12-31

申请号：US14751400

申请日：2015-06-26

申请人： Shih-Chuan Tsai ,  Ching-Chang Yang

发明人： Shih-Chuan Tsai ,  Ching-Chang Yang

IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K3/10 ,  H05K3/14 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K3/4664 ,  H05K3/125 ,  H05K3/1258 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/465 ,  H05K2201/09845 ,  H05K2203/1572

摘要： The present disclosure provides a printed circuit board and a method for fabricating the same, and an apparatus for fabricating printed circuit board. The printed circuit board includes a substrate having an upper surface; a first trench in the upper surface of the substrate; a first via formed in the first trench and penetrating through the substrate; and a first conductive layer disposed in the first trench and the first via, the first trench is electrically connect to the first via. A method for fabricating the printed circuit board and an apparatus for fabricating the printed circuit board is also provided.

摘要翻译： 本公开提供了一种印刷电路板及其制造方法，以及一种用于制造印刷电路板的装置。 印刷电路板包括具有上表面的基板; 在衬底的上表面中的第一沟槽; 形成在第一沟槽中并穿透基板的第一通孔; 以及设置在所述第一沟槽和所述第一通孔中的第一导电层，所述第一沟槽电连接到所述第一通孔。 还提供了制造印刷电路板的方法和用于制造印刷电路板的装置。

公开(公告)号：US08978244B2

公开(公告)日：2015-03-17

申请号：US13116001

申请日：2011-05-26

申请人： Xue-Jun Cai ,  Zhi-Yong Li ,  Chao Liu

发明人： Xue-Jun Cai ,  Zhi-Yong Li ,  Chao Liu

IPC分类号： H05K3/20 ,  H05K3/46

CPC分类号： H05K3/4697 ,  H05K3/462 ,  H05K3/4647 ,  H05K2203/061 ,  H05K2203/0733 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

摘要： A method for manufacturing a printed circuit board with cavity includes following steps. First, a first substrate is provided. The first substrate includes a first electrically conductive layer defining an exposed portion and a laminating portion. Second, a second substrate is provided. The second substrate includes an unwanted portion corresponding to the exposed portion and a preserving portion. Third, a first annular bump surrounding the exposed portion is formed. Fourth, a second annular bump surrounding the unwanted portion is formed. Fifth, a first adhesive layer defining an opening is provided. Sixth, the first and second substrates are laminated to the first adhesive layer, the exposed portion and the unwanted portion are exposed in the opening, and the second annular bump is in contact with the first annular bump. Seventh, the unwanted portion is removed and a cavity is defined, the exposed portion is exposed in the cavity.

摘要翻译： 制造具有空腔的印刷电路板的方法包括以下步骤。 首先，提供第一基板。 第一衬底包括限定暴露部分的第一导电层和层压部分。 其次，设置第二基板。 第二基板包括对应于暴露部分的不期望部分和保留部分。 第三，形成围绕暴露部分的第一环形凸块。 第四，形成围绕不想要的部分的第二环形凸起。 第五，提供限定开口的第一粘合剂层。 第六，将第一和第二基板层叠到第一粘合剂层上，将暴露部分和不想要的部分暴露在开口中，并且第二环形凸块与第一环形凸起接触。 第七，去除不想要的部分并且限定空腔，暴露部分暴露在空腔中。

公开(公告)号：US20140313681A1

公开(公告)日：2014-10-23

申请号：US14321030

申请日：2014-07-01

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

摘要： An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

摘要翻译： 公开了一种电子部件嵌入式基板。 电子部件嵌入式基板包括第一基板，第二基板，电子部件，电连接部件和密封部件。 还公开了一种制造电子部件嵌入式基板的方法。 该方法包括将电子部件安装到第一基板上，通过电连接部件将第二基板层压在第一基板上; 以及用密封构件填充第一基板和第二基板之间的空间以密封电子部件。

公开(公告)号：US08756805B2

公开(公告)日：2014-06-24

申请号：US13256114

申请日：2010-03-09

申请人： Norihiro Yamaguchi ,  Hiroaki Umeda ,  Ken Yukawa

发明人： Norihiro Yamaguchi ,  Hiroaki Umeda ,  Ken Yukawa

IPC分类号： H01K3/10

CPC分类号： H05K3/46 ,  H01B1/22 ,  H05K1/0298 ,  H05K1/095 ,  H05K3/0032 ,  H05K3/4069 ,  H05K3/462 ,  H05K2201/0191 ,  H05K2201/0272 ,  H05K2201/0355 ,  H05K2201/10378 ,  H05K2203/0278 ,  H05K2203/0425 ,  H05K2203/1105 ,  H05K2203/111 ,  H05K2203/1194 ,  H05K2203/1461 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of manufacturing a multilayer board, including: forming a hole through a pre-preg by laser, filling the hole with conductive paste containing a resin component and metal powder, and arranging copper layer portions of patterned boards on and under the filled conductive paste and pressing the same, wherein in the conductive paste at least surface layers of the different metal powders are melted and alloyed, the pre-preg has a ratio A/B of at least 10 before being subjected to preheating, where A is a storage modulus at an inflection point where the storage modulus changes from increasing to decreasing and B is a storage modulus at an inflection point where the storage modulus changes from decreasing to increasing in a temperature rising from 60 to 200 degree C., and preheating the pre-preg before the drilling step to reduce the ratio A/B to below 10.

摘要翻译： 一种制造多层板的方法，包括：通过激光预预处理形成孔，用含有树脂成分和金属粉末的导电膏填充孔，并且在填充的导电糊料的上方和下方布置图案化板的铜层部分 并且对其进行压制，其中在所述导电浆料中，所述不同金属粉末的至少表面层熔融并合金化，所述预浸料在进行预热之前的比率A / B为至少10，其中A为储能模量 在储能模量从增加到降低的拐点处，B是在从60℃升至200℃的温度下储能模量从降低到升高的拐点处的储能模量，并预热预浸料 在钻井步骤之前将A / B比例降低到10以下。