公开(公告)号：US20120023388A1

公开(公告)日：2012-01-26

申请号：US12842676

申请日：2010-07-23

申请人： Chi-Lin Liu ,  Yi-Tzu Chen ,  Chung-Cheng Chou

发明人： Chi-Lin Liu ,  Yi-Tzu Chen ,  Chung-Cheng Chou

IPC分类号： G06F11/10

CPC分类号： G06F12/0875 ,  G06F11/1064 ,  H03M13/098

摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.

摘要翻译： 一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。 比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。 当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。 该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

公开(公告)号：US20120098582A1

公开(公告)日：2012-04-26

申请号：US12908602

申请日：2010-10-20

申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yi-Tzu Chen

发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yi-Tzu Chen

IPC分类号： H03K3/356 ,  H03K3/01

CPC分类号： H03K3/356121

摘要： A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.

摘要翻译： 触发器电路包括预充电电路，当接收到的时钟信号为低电平时，该充电电路输出高电平信号。 当时钟信号为高电平时，延迟时钟输入电路产生与输入信号相同值的延迟时钟输入受控信号。 充电保持器电路在接收到充电信号和延迟的时钟输入受控信号时产生一个充电保持信号，当时钟信号为低电平时，该充电信号等于充电信号，并且当时钟信号为高电平时等于延迟的时钟输入受控信号。 分离器电路可以接收电荷保持信号和时钟信号并产生反向电荷保持信号。 存储电路被配置为接收反转的保持电荷信号，当前状态信号和反相的当前状态信号，并且生成当前状态信号和反相的当前状态信号。

公开(公告)号：US08416002B2

公开(公告)日：2013-04-09

申请号：US12908602

申请日：2010-10-20

申请人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yi-Tzu Chen

发明人： Chi-Lin Liu ,  Chung-Cheng Chou ,  Yi-Tzu Chen

IPC分类号： H03K3/356

CPC分类号： H03K3/356121

摘要： A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.

摘要翻译： 触发器电路包括预充电电路，当接收到的时钟信号为低电平时，该充电电路输出高电平信号。 当时钟信号为高电平时，延迟时钟输入电路产生与输入信号相同值的延迟时钟输入受控信号。 充电保持器电路在接收到充电信号和延迟的时钟输入受控信号时产生一个充电保持信号，当时钟信号为低电平时，该充电信号等于充电信号，并且当时钟信号为高电平时等于延迟的时钟输入受控信号。 分离器电路可以接收电荷保持信号和时钟信号并产生反向电荷保持信号。 存储电路被配置为接收反转的保持电荷信号，当前状态信号和反相的当前状态信号，并且生成当前状态信号和反相的当前状态信号。

公开(公告)号：US08359528B2

公开(公告)日：2013-01-22

申请号：US12842676

申请日：2010-07-23

申请人： Chi-Lin Liu ,  Yi-Tzu Chen ,  Chung-Cheng Chou

发明人： Chi-Lin Liu ,  Yi-Tzu Chen ,  Chung-Cheng Chou

IPC分类号： H03M13/00

CPC分类号： G06F12/0875 ,  G06F11/1064 ,  H03M13/098

摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.

摘要翻译： 一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。 比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。 当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。 该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

公开(公告)号：US08405441B2

公开(公告)日：2013-03-26

申请号：US13070868

申请日：2011-03-24

申请人： Chien-Kuo Su ,  Yi-Tzu Chen ,  Chung-Cheng Chou

发明人： Chien-Kuo Su ,  Yi-Tzu Chen ,  Chung-Cheng Chou

IPC分类号： H03K3/356

CPC分类号： H03K3/012 ,  H03K3/356121 ,  H03K3/356173

摘要： A latch circuit includes an output driver electrically coupled with a circuit. The circuit is electrically coupled with the output driver through a first path and a second path. The circuit is configured to receive a data signal. The circuit is configured to divert a signal of the output driver through the first path at a falling edge of the data signal. The circuit is configured to divert the signal of the output driver through the second path at a rising edge of the data signal.

摘要翻译： 锁存电路包括与电路电耦合的输出驱动器。 电路通过第一路径和第二路径与输出驱动器电耦合。 电路被配置为接收数据信号。 电路被配置为在数据信号的下降沿通过第一路径转移输出驱动器的信号。 电路被配置为在数据信号的上升沿通过第二路径转移输出驱动器的信号。

公开(公告)号：US08116149B2

公开(公告)日：2012-02-14

申请号：US12687571

申请日：2010-01-14

申请人： Yi-Tzu Chen ,  Chia-Wei Su ,  Ming-Zhang Kuo ,  Chung-Cheng Chou

发明人： Yi-Tzu Chen ,  Chia-Wei Su ,  Ming-Zhang Kuo ,  Chung-Cheng Chou

IPC分类号： G11C7/06

CPC分类号： G11C8/12 ,  G11C11/413

摘要： Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.

摘要翻译： 描述用于向存储器发送和接收小的摆动差分电压数据的电路和方法。 多个存储单元形成为多个存储体中的阵列。 每个存储体耦合到跨越存储器延伸的一对小的摆动差分电压全局位线。 小信号写驱动器电路耦合到全局位线并且被配置为在写周期期间在全局位线上输出小信号差分电压。 全局读出放大器耦合到全局位线对并被配置为在读取周期期间在数据线上输出全摆幅电压。 公开了向存储器单元提供小的摆动全局位线信号的方法。 在存储器内使用小的摆幅差分电压信号可以降低功耗并缩短存储周期时间。

公开(公告)号：US20100260002A1

公开(公告)日：2010-10-14

申请号：US12687571

申请日：2010-01-14

申请人： Yi-Tzu Chen ,  Chia-Wei Su ,  Ming-Zhang Kuo ,  Chung-Cheng Chou

发明人： Yi-Tzu Chen ,  Chia-Wei Su ,  Ming-Zhang Kuo ,  Chung-Cheng Chou

IPC分类号： G11C7/02 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C11/413

摘要： Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time.

摘要翻译： 描述用于向存储器发送和接收小的摆动差分电压数据的电路和方法。 多个存储单元形成为多个存储体中的阵列。 每个存储体耦合到跨越存储器延伸的一对小的摆动差分电压全局位线。 小信号写驱动器电路耦合到全局位线并且被配置为在写周期期间在全局位线上输出小信号差分电压。 全局读出放大器耦合到全局位线对并被配置为在读取周期期间在数据线上输出全摆幅电压。 公开了向存储器单元提供小的摆动全局位线信号的方法。 在存储器内使用小的摆幅差分电压信号可以降低功耗并缩短存储周期时间。

公开(公告)号：US09295874B1

公开(公告)日：2016-03-29

申请号：US14551700

申请日：2014-11-24

申请人： Yi-Tzu Chen

发明人： Yi-Tzu Chen

IPC分类号： A63B22/04 ,  A63B22/00 ,  A63B69/18 ,  A63B22/06 ,  A63B21/015

CPC分类号： A63B22/0664 ,  A63B21/005 ,  A63B21/015 ,  A63B21/225 ,  A63B22/001 ,  A63B22/0023 ,  A63B22/205 ,  A63B24/0087 ,  A63B2022/0676 ,  A63B2022/0682

摘要： An elliptical trainer has a base, two sliding assemblies, a slope adjusting mechanism, and two stride adjusting mechanisms. A transverse diameter of an elliptical path that a user exercises along can be adjusted by driving the slope adjusting mechanism, so as to adjust each stride of the user. A slope of the elliptical path can also be adjusted by driving the stride adjusting mechanisms, so as to provide climbing exercise effects. The elliptical trainer can be easily adjusted to form different exercise modes and intensities. The user's desire for exercising on the elliptical trainer can be increased accordingly.

摘要翻译： 椭圆训练机具有底座，两个滑动组件，斜坡调节机构和两个步幅调节机构。 用户行使的椭圆形路径的横向直径可以通过驱动斜面调节机构来调整，以便调整用户的每一步。 也可以通过驱动步幅调整机构来调整椭圆路径的斜率，以提供攀爬运动效果。 椭圆教练可以轻松调整，形成不同的运动模式和强度。 可以相应地增加用户对椭圆训练器的锻炼欲望。

公开(公告)号：US08556780B2

公开(公告)日：2013-10-15

申请号：US13078594

申请日：2011-04-01

申请人： Yi-Tzu Chen

发明人： Yi-Tzu Chen

IPC分类号： A63B21/00

CPC分类号： A63B21/023 ,  A63B21/00072 ,  A63B21/0421 ,  A63B21/055 ,  A63B21/4015 ,  A63B21/4033 ,  A63B21/4047 ,  A63B22/14 ,  A63B23/0227 ,  A63B23/0233 ,  A63B2208/0238

摘要： A multifunctional linked fitness equipment has an elongated bottom, a seat stand, a front support frame seat pivotally mounted on a front end of the elongated bottom, a rear support frame seat pivotally mounted on a rear end of the seat stand, a link pivotally mounted between the front support frame seat and the rear support frame seat, a front support frame pivotally mounted on the elongated bottom and the front support frame seat, a rear support frame pivotally mounted on the elongated bottom and the rear support frame seat, and at least one resilient member mounted between the rear support frame seat and the elongated bottom. By combining or detaching the front support frame, the rear support frame or the seat stand with or from positioning pins, the fitness equipment can be utilized to selectively exercise the abdominal muscles and the legs based on the users' demand.

摘要翻译： 一种多功能连接健身器材具有细长的底部，座椅支架，可枢转地安装在细长底部的前端上的前支撑框架座椅，可枢转地安装在座椅支架的后端上的后支撑框架座，可枢转地安装的连杆 在前支撑框架座和后支撑框架座之间，可枢转地安装在细长底部上的前支撑框架和前支撑框架座，可枢转地安装在细长底部和后支撑框架座上的后支撑框架，并且至少 安装在后支撑框架座和细长底部之间的一个弹性构件。 通过将前支撑框架，后支撑框架或座椅支架与定位销组合或分离，健身器材可以用于根据用户的需求选择性地锻炼腹肌和腿部。

公开(公告)号：US09275721B2

公开(公告)日：2016-03-01

申请号：US12847647

申请日：2010-07-30

申请人： Yi-Tzu Chen ,  Bin-Hau Lo ,  Tsai-Hsin Lai ,  Pey-Huey Chen ,  Hau-Tai Shieh

发明人： Yi-Tzu Chen ,  Bin-Hau Lo ,  Tsai-Hsin Lai ,  Pey-Huey Chen ,  Hau-Tai Shieh

IPC分类号： G11C11/40 ,  G11C11/4097 ,  G11C5/06

CPC分类号： G11C11/4097 ,  G11C5/063

摘要： Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.

摘要翻译： 公开了用于提供具有缩短的读取访问时间的高密度存储器阵列的装置和方法。 多个分割位线沿着相邻存储器位单元的列排列。 多输入读出放大器耦合到多个分割位线。 多分割位线上的负载减小，并且存储器阵列的相应读取速度比现有技术增强。 读出放大器和存储器单元具有公共单元间距布局高度，从而由于使用多个分割位线和读出放大器而不会产生硅面积损失。 提高内存阵列效率。