公开(公告)号：US08587368B2

公开(公告)日：2013-11-19

申请号：US13460432

申请日：2012-04-30

申请人： Chi-Ping Yao ,  Wen-Shen Chou

发明人： Chi-Ping Yao ,  Wen-Shen Chou

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.

摘要翻译： 一种方法包括产生第一电流，其中第一电流流过第一电阻器和第一双极晶体管。 第一电阻器的第一端串联连接到第一双极晶体管的发射极 - 集电极路径，并且电阻器的第二端连接到运算放大器的输入端。 产生第二电流以流过连接到运算放大器的输入端的第二电阻器。 第二双极晶体管的发射极连接到第一双极晶体管的基极，其中第二双极晶体管的基极和集电极连接到VSS。 添加第一和第二电流以产生第三电流，其被镜像以产生与第三电流成比例的第四电流。 第四电流通过第三电阻器传导以产生输出参考电压。

公开(公告)号：US08169256B2

公开(公告)日：2012-05-01

申请号：US12617933

申请日：2009-11-13

申请人： Chi-Ping Yao ,  Wen-Shen Chou

发明人： Chi-Ping Yao ,  Wen-Shen Chou

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A circuit includes an operational amplifier including a first input and a second input. A first resistor has a first end coupled to the first input. A first bipolar transistor includes a first emitter coupled to a second end of the first resistor, and a first base. A second bipolar transistor includes a second emitter coupled to the second input, and a second base. A third bipolar transistor includes a third emitter coupled to the first base, a first collector, and a third base connected to the first collector. A fourth bipolar transistor includes a fourth emitter coupled to the second base, a second collector, and a fourth base connected to the second collector. A second resistor is coupled to the first input, wherein the second resistor is parallel to the first resistor and the first bipolar transistor.

摘要翻译： 电路包括运算放大器，包括第一输入和第二输入。 第一电阻器具有耦合到第一输入的第一端。 第一双极晶体管包括耦合到第一电阻器的第二端的第一发射极和第一基极。 第二双极晶体管包括耦合到第二输入端的第二发射极和第二基极。 第三双极晶体管包括耦合到第一基极的第三发射极，第一集电极和连接到第一集电极的第三基极。 第四双极晶体管包括耦合到第二基极的第四发射极，第二集电极和连接到第二集电极的第四基极。 第二电阻器耦合到第一输入端，其中第二电阻器平行于第一电阻器和第一双极晶体管。

公开(公告)号：US20120212208A1

公开(公告)日：2012-08-23

申请号：US13460432

申请日：2012-04-30

申请人： Chi-Ping Yao ,  Wen-Shen Chou

发明人： Chi-Ping Yao ,  Wen-Shen Chou

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.

摘要翻译： 一种方法包括产生第一电流，其中第一电流流过第一电阻器和第一双极晶体管。 第一电阻器的第一端串联连接到第一双极晶体管的发射极 - 集电极路径，并且电阻器的第二端连接到运算放大器的输入端。 产生第二电流以流过连接到运算放大器的输入端的第二电阻器。 第二双极晶体管的发射极连接到第一双极晶体管的基极，其中第二双极晶体管的基极和集电极连接到VSS。 添加第一和第二电流以产生第三电流，其被镜像以产生与第三电流成比例的第四电流。 第四电流通过第三电阻器传导以产生输出参考电压。

公开(公告)号：US20100207597A1

公开(公告)日：2010-08-19

申请号：US12617933

申请日：2009-11-13

申请人： Chi-Ping Yao ,  Wen-Shen Chou

发明人： Chi-Ping Yao ,  Wen-Shen Chou

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A circuit includes an operational amplifier including a first input and a second input. A first resistor has a first end coupled to the first input. A first bipolar transistor includes a first emitter coupled to a second end of the first resistor, and a first base. A second bipolar transistor includes a second emitter coupled to the second input, and a second base. A third bipolar transistor includes a third emitter coupled to the first base, a first collector, and a third base connected to the first collector. A fourth bipolar transistor includes a fourth emitter coupled to the second base, a second collector, and a fourth base connected to the second collector. A second resistor is coupled to the first input, wherein the second resistor is parallel to the first resistor and the first bipolar transistor.

摘要翻译： 电路包括运算放大器，包括第一输入和第二输入。 第一电阻器具有耦合到第一输入的第一端。 第一双极晶体管包括耦合到第一电阻器的第二端的第一发射极和第一基极。 第二双极晶体管包括耦合到第二输入端的第二发射极和第二基极。 第三双极晶体管包括耦合到第一基极的第三发射极，第一集电极和连接到第一集电极的第三基极。 第四双极晶体管包括耦合到第二基极的第四发射极，第二集电极和连接到第二集电极的第四基极。 第二电阻器耦合到第一输入端，其中第二电阻器平行于第一电阻器和第一双极晶体管。

公开(公告)号：US08476971B2

公开(公告)日：2013-07-02

申请号：US12889492

申请日：2010-09-24

申请人： Yung-Chow Peng ,  Wen-Shen Chou ,  Ching-Ho Chang ,  Wan-Te Chen

发明人： Yung-Chow Peng ,  Wen-Shen Chou ,  Ching-Ho Chang ,  Wan-Te Chen

IPC分类号： G06G7/12

CPC分类号： G09G3/3688 ,  G09G2310/027

摘要： A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.

摘要翻译： 驱动器利用运算放大器的端子的选择性偏置来减小运算放大器输出中的偏移。 每个运算放大器输入包括包括NMOS晶体管和PMOS晶体管的差分输入对晶体管。 在输入电压范围的低端和高端，这些晶体管选择性地和单独地耦合到标准输入或偏置为导通，以便补偿偏移补偿。 晶体管以常规方式偏置，用于在电压范围的低端和高端之间的输入电压。

公开(公告)号：US20100141497A1

公开(公告)日：2010-06-10

申请号：US12331049

申请日：2008-12-09

申请人： Robit Yang ,  Ying-Chi Hsu ,  You-Cheng Xiao ,  Wen-Shen Chou

发明人： Robit Yang ,  Ying-Chi Hsu ,  You-Cheng Xiao ,  Wen-Shen Chou

IPC分类号： H03M1/66

CPC分类号： H03M1/0651 ,  H03M1/0648 ,  H03M1/682 ,  H03M1/687 ,  H03M1/747

摘要： A digital-to-analog converter (DAC) for converting a digital signal to an analog signal includes a first thermometer decoder and a second thermometer decoder. The first thermometer decoder is configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code. The second thermometer decoder is configured to decode middle bits of the digital signal to generate a second thermometer code. The DAC further includes a plurality of macro cells with each controlled by one bit of the first thermometer code. The plurality of macro cells is configured to provide a first analog signal according to the first thermometer code. The DAC further includes a macro cell configured to provide a second analog signal according to the second thermometer code. The macro cell is further configured to provide a third analog signal according to least-significant bits (LSBs) of the digital signal.

摘要翻译： 用于将数字信号转换为模拟信号的数模转换器（DAC）包括第一温度计解码器和第二温度计解码器。 第一温度计解码器被配置为解码数字信号的最高有效位（MSB），以产生第一温度计代码。 第二温度计解码器被配置为解码数字信号的中间位以产生第二温度计代码。 DAC还包括多个宏单元，每个宏单元由第一温度计代码的一位控制。 多个宏小区被配置为根据第一温度计代码提供第一模拟信号。 DAC还包括配置成根据第二温度计代码提供第二模拟信号的宏单元。 宏小区还被配置为根据数字信号的最低有效位（LSB）提供第三模拟信号。

公开(公告)号：US08719755B2

公开(公告)日：2014-05-06

申请号：US13562638

申请日：2012-07-31

申请人： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

发明人： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

摘要翻译： 除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。 例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。 在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。 例如，第一图案密度和第二图案密度是门密度和/或多密度。 为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。 以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。

公开(公告)号：US20110241915A1

公开(公告)日：2011-10-06

申请号：US13159856

申请日：2011-06-14

申请人： Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

发明人： Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

IPC分类号： H03M1/10

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

摘要： A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.

摘要翻译： 提供了一种将数字信号转换为模拟信号的系统和方法。 本公开提供了一种数模转换器（DAC），其可以将大位值数字信号转换为对应的模拟信号。 根据实施例，一种方法包括：通过多个子DAC接收数字信号的部分; 通过所述多个子DAC将所述数字信号的所述部分转换成相应的模拟信号; 偏置所述多个子DAC中的一个或多个; 以及通过一个或多个校准元件校准数字信号的部分。

公开(公告)号：US20110089916A1

公开(公告)日：2011-04-21

申请号：US12857092

申请日：2010-08-16

申请人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Ying-Chih Hsu ,  Guang-Cheng Wang ,  Wen-Shen Chou

发明人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Ying-Chih Hsu ,  Guang-Cheng Wang ,  Wen-Shen Chou

IPC分类号： G05F1/10

CPC分类号： G05F1/575 ,  H02M3/07 ,  H02M2001/0045

摘要： Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed.

摘要翻译： 本发明的实施例涉及LDO调节器。 在一个实施例中，放大器驱动主源跟随器的栅极和至少一个从源极跟随器的栅极以形成LDO调节器。 在替代实施例中，电荷泵驱动主源极跟随器以形成调节器。 附加的从源跟随器可以与电荷泵和主源极跟随器一起使用，以改善调节器的性能。 还公开了其他实施例。

公开(公告)号：US09158883B2

公开(公告)日：2015-10-13

申请号：US13569717

申请日：2012-08-08

申请人： Yung-Chow Peng ,  Wen-Shen Chou ,  Jaw-Juinn Horng

发明人： Yung-Chow Peng ,  Wen-Shen Chou ,  Jaw-Juinn Horng

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  G06F17/5081

摘要： This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

摘要翻译： 本公开涉及制造半导体器件的方法。 该方法包括将半导体器件的示意图设计与半导体器件的布局设计进行比较。 该方法还包括基于布局设计生成布局样式信息，并基于布局设计和原理图设计生成阵列边缘信息。 该方法还包括使用布局样式信息和阵列边缘信息来选择性地修改使用智能虚拟插入的布局设计。 该方法还包括使用布局样式信息和阵列边缘信息对修改的布局设计执行设计规则检查。 本公开还涉及一种用于制造半导体器件和半导体器件的系统。