Decoder Architecture with Sub-Thermometer Codes for DACs
    1.
    发明申请
    Decoder Architecture with Sub-Thermometer Codes for DACs 有权
    用于DAC的子温度计代码的解码器架构

    公开(公告)号:US20100141497A1

    公开(公告)日:2010-06-10

    申请号:US12331049

    申请日:2008-12-09

    IPC分类号: H03M1/66

    摘要: A digital-to-analog converter (DAC) for converting a digital signal to an analog signal includes a first thermometer decoder and a second thermometer decoder. The first thermometer decoder is configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code. The second thermometer decoder is configured to decode middle bits of the digital signal to generate a second thermometer code. The DAC further includes a plurality of macro cells with each controlled by one bit of the first thermometer code. The plurality of macro cells is configured to provide a first analog signal according to the first thermometer code. The DAC further includes a macro cell configured to provide a second analog signal according to the second thermometer code. The macro cell is further configured to provide a third analog signal according to least-significant bits (LSBs) of the digital signal.

    摘要翻译: 用于将数字信号转换为模拟信号的数模转换器(DAC)包括第一温度计解码器和第二温度计解码器。 第一温度计解码器被配置为解码数字信号的最高有效位(MSB),以产生第一温度计代码。 第二温度计解码器被配置为解码数字信号的中间位以产生第二温度计代码。 DAC还包括多个宏单元,每个宏单元由第一温度计代码的一位控制。 多个宏小区被配置为根据第一温度计代码提供第一模拟信号。 DAC还包括配置成根据第二温度计代码提供第二模拟信号的宏单元。 宏小区还被配置为根据数字信号的最低有效位(LSB)提供第三模拟信号。

    Decoder architecture with sub-thermometer codes for DACs
    2.
    发明授权
    Decoder architecture with sub-thermometer codes for DACs 有权
    DAC的子温度计代码解码器架构

    公开(公告)号:US08013770B2

    公开(公告)日:2011-09-06

    申请号:US12331049

    申请日:2008-12-09

    IPC分类号: H03M1/66

    摘要: A digital-to-analog converter (DAC) for converting a digital signal to an analog signal includes a first thermometer decoder and a second thermometer decoder. The first thermometer decoder is configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code. The second thermometer decoder is configured to decode middle bits of the digital signal to generate a second thermometer code. The DAC further includes a plurality of macro cells with each controlled by one bit of the first thermometer code. The plurality of macro cells is configured to provide a first analog signal according to the first thermometer code. The DAC further includes a macro cell configured to provide a second analog signal according to the second thermometer code. The macro cell is further configured to provide a third analog signal according to least-significant bits (LSBs) of the digital signal.

    摘要翻译: 用于将数字信号转换为模拟信号的数模转换器(DAC)包括第一温度计解码器和第二温度计解码器。 第一温度计解码器被配置为解码数字信号的最高有效位(MSB),以产生第一温度计代码。 第二温度计解码器被配置为解码数字信号的中间位以产生第二温度计代码。 DAC还包括多个宏单元,每个宏单元由第一温度计代码的一位控制。 多个宏小区被配置为根据第一温度计代码提供第一模拟信号。 DAC还包括配置成根据第二温度计代码提供第二模拟信号的宏单元。 宏小区还被配置为根据数字信号的最低有效位(LSB)提供第三模拟信号。

    Method and apparatus for word line decoder layout
    4.
    发明授权
    Method and apparatus for word line decoder layout 有权
    字线解码器布局的方法和装置

    公开(公告)号:US08837250B2

    公开(公告)日:2014-09-16

    申请号:US12839490

    申请日:2010-07-20

    IPC分类号: G11C8/10

    CPC分类号: G11C8/10 G11C11/413

    摘要: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

    摘要翻译: 字线解码器包括多个驱动器电路,设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。 字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。 字线解码器还包括耦合到每个主输入线的本地解码线。 字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。 集群解码线耦合到解码线。 字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

    Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance
    5.
    发明授权
    Semiconductor device for word line driver with efficient routing of conductor for decreased gate resistance 有权
    用于字线驱动器的半导体器件,具有用于降低栅极电阻的导体的有效布线

    公开(公告)号:US08692333B2

    公开(公告)日:2014-04-08

    申请号:US12855004

    申请日:2010-08-12

    IPC分类号: H01L29/76

    摘要: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

    摘要翻译: 半导体器件包括第一,第二和第三。 第一导体是形成在衬底上方并具有接触的氧化物区域上方的栅极导体。 第二导体耦合到触点并延伸穿过氧化物区域的宽度。 第二导体的电阻低于栅极导体。 第三导体是字线导体。 第二个导体被路由到不与字线导体相交。