公开(公告)号：US20130175638A1

公开(公告)日：2013-07-11

申请号：US13346411

申请日：2012-01-09

申请人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.

摘要翻译： 一种方法包括在第一半导体鳍上形成包括栅电极的栅叠层。 栅极电极包括在第一半导体鳍片的中间部分上并对准的部分。 第二半导体鳍片位于栅电极的一侧，并且不延伸至栅电极下方。 第一和第二半导体散热片彼此间隔开并平行。 蚀刻第一半导体鳍片和第二半导体鳍片的端部。 进行外延以形成外延区域，其包括延伸到由第一半导体鳍片的蚀刻的第一端部分留下的第一空间的第一部分和延伸到由蚀刻的第二半导体鳍留下的第二空间的第二部分。 在外延区域形成第一源极/漏极区域。

公开(公告)号：US08609499B2

公开(公告)日：2013-12-17

申请号：US13346411

申请日：2012-01-09

申请人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.

公开(公告)号：US08759184B2

公开(公告)日：2014-06-24

申请号：US13346445

申请日：2012-01-09

申请人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

摘要翻译： 一种方法包括提供彼此平行的多个半导体鳍片，并且包括两个边缘鳍片和两个边缘鳍片之间的中心鳍片。 蚀刻两个边缘翅片中的每一个的中间部分，并且中心翅片不被蚀刻。 栅极电介质形成在中心翅片的顶表面和侧壁上。 在栅极电介质上形成栅电极。 两个边缘翅片的端部和中心翅片的端部是凹进的。 进行外延以形成外延区域，其中由两个边缘翅片的端部留下的空间生长的外延材料与从中心翅片的端部留下的空间生长的外延材料合并，形成外延 地区。 源极/漏极区域形成在外延区域中。

公开(公告)号：US20130175584A1

公开(公告)日：2013-07-11

申请号：US13346445

申请日：2012-01-09

申请人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Shen Chang

发明人： Chia-Cheng Ho ,  Tzu-Chiang Chen ,  Yi-Tang Lin ,  Chih-Shen Chang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

摘要翻译： 一种方法包括提供彼此平行的多个半导体鳍片，并且包括两个边缘鳍片和两个边缘鳍片之间的中心鳍片。 蚀刻两个边缘翅片中的每一个的中间部分，并且中心翅片不被蚀刻。 栅极电介质形成在中心翅片的顶表面和侧壁上。 在栅极电介质上形成栅电极。 两个边缘翅片的端部和中心翅片的端部是凹进的。 进行外延以形成外延区域，其中由两个边缘翅片的端部留下的空间生长的外延材料与从中心翅片的端部留下的空间生长的外延材料合并，形成外延 地区。 源极/漏极区域形成在外延区域中。

公开(公告)号：US20130166248A1

公开(公告)日：2013-06-27

申请号：US13336306

申请日：2011-12-23

申请人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

发明人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

IPC分类号： G06F15/00 ,  H01L21/66

CPC分类号： H01L22/12 ,  G01B7/06 ,  H01L21/823431 ,  H01L22/34

摘要： A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

摘要翻译： 用于估计其它半导体器件中的外延生长的半导体材料的高度的方法和装置。 该方法包括在第一半导体器件上外延生长半导体材料的第一，第二和第三部分，测量半导体材料的第三部分的高度和半导体材料的第一或第二部分的高度，测量第一饱和电流通过 半导体材料的第一和第二部分，测量通过半导体材料的第一和第三部分的第二饱和电流，以及制备相对于半导体材料的第一或第二部分的高度和第二饱和度的第一饱和电流的模型 电流相对于半导体材料的第一和第三部分的高度的平均值。 该模型用于估计其它半导体器件中外延生长的半导体材料的高度。

公开(公告)号：US08906710B2

公开(公告)日：2014-12-09

申请号：US13336306

申请日：2011-12-23

申请人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

发明人： Chih-Sheng Chang ,  Chia-Cheng Ho ,  Yi-Tang Lin

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  G01B7/06 ,  H01L21/823431 ,  H01L22/34

摘要： A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

摘要翻译： 用于估计其它半导体器件中的外延生长的半导体材料的高度的方法和装置。 该方法包括在第一半导体器件上外延生长半导体材料的第一，第二和第三部分，测量半导体材料的第三部分的高度和半导体材料的第一或第二部分的高度，测量第一饱和电流通过 半导体材料的第一和第二部分，测量通过半导体材料的第一和第三部分的第二饱和电流，以及制备相对于半导体材料的第一或第二部分的高度和第二饱和度的第一饱和电流的模型 电流相对于半导体材料的第一和第三部分的高度的平均值。 该模型用于估计其它半导体器件中外延生长的半导体材料的高度。

公开(公告)号：US20130174103A1

公开(公告)日：2013-07-04

申请号：US13339646

申请日：2011-12-29

申请人： Ming-Feng Shieh ,  Yi-Tang Lin ,  Chia-Cheng Ho ,  Chih-Sheng Chang

发明人： Ming-Feng Shieh ,  Yi-Tang Lin ,  Chia-Cheng Ho ,  Chih-Sheng Chang

IPC分类号： G06F17/50

CPC分类号： H01L21/823431 ,  G03F1/38 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70466 ,  H01L21/845

摘要： Methods for forming a single fin fin-like field effect transistor (FinFET) device are disclosed. An exemplary method includes providing a main mask layout and a trim mask layout to form fins of a fin-like field effect transistor (FinFET) device, wherein the main mask layout includes a first masking feature and the trim mask layout includes a second masking feature that defines at least two fins, the first masking feature and the second masking feature having a spatial relationship; and modifying the main mask layout based on the spatial relationship between the first masking feature and the second masking feature, wherein the modifying the main mask layout includes modifying the first masking feature such that a single fin FinFET device is formed using the modified main mask layout and the trim mask layout.

摘要翻译： 公开了形成单个翅片状场效应晶体管（FinFET）器件的方法。 一种示例性方法包括提供主掩模布局和修剪掩模布局以形成鳍状场效应晶体管（FinFET）器件的鳍，其中主掩模布局包括第一掩蔽特征，并且修剪蒙版布局包括第二掩蔽特征 其限定至少两个鳍，所述第一掩蔽特征和所述第二掩蔽特征具有空间关系; 以及基于所述第一掩蔽特征和所述第二掩蔽特征之间的空间关系来修改所述主掩模布局，其中所述修改所述主掩模布局包括修改所述第一掩蔽特征，使得使用所述修改的主掩模布局形成单鳍FinFET器件 和修剪蒙版布局。

公开(公告)号：US08881066B2

公开(公告)日：2014-11-04

申请号：US13339646

申请日：2011-12-29

申请人： Ming-Feng Shieh ,  Yi-Tang Lin ,  Chia-Cheng Ho ,  Chih-Sheng Chang

发明人： Ming-Feng Shieh ,  Yi-Tang Lin ,  Chia-Cheng Ho ,  Chih-Sheng Chang

IPC分类号： G06F17/50

CPC分类号： H01L21/823431 ,  G03F1/38 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70466 ,  H01L21/845

摘要： Methods for forming a single fin fin-like field effect transistor (FinFET) device are disclosed. An exemplary method includes providing a main mask layout and a trim mask layout to form fins of a fin-like field effect transistor (FinFET) device, wherein the main mask layout includes a first masking feature and the trim mask layout includes a second masking feature that defines at least two fins, the first masking feature and the second masking feature having a spatial relationship; and modifying the main mask layout based on the spatial relationship between the first masking feature and the second masking feature, wherein the modifying the main mask layout includes modifying the first masking feature such that a single fin FinFET device is formed using the modified main mask layout and the trim mask layout.

摘要翻译： 公开了形成单个翅片状场效应晶体管（FinFET）器件的方法。 一种示例性方法包括提供主掩模布局和修剪掩模布局以形成鳍状场效应晶体管（FinFET）器件的鳍，其中主掩模布局包括第一掩蔽特征，并且修剪蒙版布局包括第二掩蔽特征 其限定至少两个鳍，所述第一掩蔽特征和所述第二掩蔽特征具有空间关系; 以及基于所述第一掩蔽特征和所述第二掩蔽特征之间的空间关系来修改所述主掩模布局，其中所述修改所述主掩模布局包括修改所述第一掩蔽特征，使得使用所述修改的主掩模布局形成单鳍FinFET器件 和修剪蒙版布局。

公开(公告)号：US08799833B2

公开(公告)日：2014-08-05

申请号：US13416907

申请日：2012-03-09

申请人： Clement Hsingjen Wann ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

发明人： Clement Hsingjen Wann ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

公开(公告)号：US08525267B2

公开(公告)日：2013-09-03

申请号：US12953148

申请日：2010-11-23

申请人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

发明人： Chien-Hsun Wang ,  Chih-Sheng Chang ,  Yi-Tang Lin ,  Ming-Feng Shieh

IPC分类号： H01L29/66

CPC分类号： H01L21/823431 ,  H01L21/845 ,  H01L27/1211

摘要： A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures.

摘要翻译： 半导体FinFET器件包括沿第一方向形成的多个栅极线和两种类型的鳍结构。 在第二方向上形成第一类型的翅片结构，以及垂直于第一类型翅片结构形成的第二类型的翅片结构。 接触孔耦合到第二类型的翅片结构中的一个或多个。