公开(公告)号：US08114715B2

公开(公告)日：2012-02-14

申请号：US12654810

申请日：2010-01-05

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/82

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20090072211A1

公开(公告)日：2009-03-19

申请号：US11898529

申请日：2007-09-13

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： G11C11/34 ,  H01L21/36

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US20060205157A1

公开(公告)日：2006-09-14

申请号：US11429070

申请日：2006-05-05

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

摘要翻译： 提供非易失性存储器。 存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。 其中介电层设置在基板上。 导电层设置在电介质层上。 隔离层设置在基板上并且邻近电介质层和导电层。 掩埋位线设置在衬底中并在隔离层下方。 隧道电介质层设置在导电层和隔离层的基板和侧壁上。 电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。 字线设置在基板上，与埋入位线交叉。

公开(公告)号：US07067375B1

公开(公告)日：2006-06-27

申请号：US11018507

申请日：2004-12-20

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

公开(公告)号：US08722469B2

公开(公告)日：2014-05-13

申请号：US11867000

申请日：2007-10-04

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/788

CPC分类号： H01L27/101 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

摘要： A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

摘要翻译： 提供了一种存储单元及其制造方法。 在该工艺中，在衬底上的导电层上形成第一电极层，然后在第一电极层上形成过渡金属层。 之后，对过渡金属层进行等离子体氧化工序，形成作为数据存储层的前体的过渡金属氧化物层，在过渡金属氧化物层上形成第二电极层。 在第二电极层，过渡金属氧化物层和第一电极层分别形成第二电极，数据存储层和第一电极之后形成存储单元。

公开(公告)号：US08642398B2

公开(公告)日：2014-02-04

申请号：US13346935

申请日：2012-01-10

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/82

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US08153485B2

公开(公告)日：2012-04-10

申请号：US13163769

申请日：2011-06-20

申请人： Erh-Kun Lai ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/8238

CPC分类号： H01L27/24 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C16/0475 ,  G11C2213/31 ,  G11C2213/51

摘要： A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer.

摘要翻译： 描述了一种制造存储器的方法。 字线在第一方向上提供。 位线沿第二方向设置。 形成连接到相应字线的顶部电极。 形成连接到相应位线的底部电极。 电阻层形成在底部电极上。 形成至少两个单独的L形衬垫，其中每个L形衬垫在L形衬套的两端具有可变电阻材料，并且每个L形衬垫耦合在顶部电极和电阻层之间。

公开(公告)号：US07667293B2

公开(公告)日：2010-02-23

申请号：US11898529

申请日：2007-09-13

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/02

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20080089111A1

公开(公告)日：2008-04-17

申请号：US11695780

申请日：2007-04-03

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

摘要： A resistance type memory device is provided. The resistance type memory device is disposed on a substrate and includes a tungsten electrode, an upper electrode, and a tungsten oxide layer. The upper electrode is disposed on the tungsten electrode. The tungsten oxide layer is sandwiched between the tungsten electrode and the upper electrode.

摘要翻译： 提供电阻型存储器件。 电阻型存储装置设置在基板上，并且包括钨电极，上电极和氧化钨层。 上电极设置在钨电极上。 氧化钨层夹在钨电极和上电极之间。