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公开(公告)号：US08623734B2
公开(公告)日：2014-01-07
申请号：US13150559
申请日：2011-06-01
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , G11C13/0004 , H01L21/31144 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/1683
摘要： An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode.
摘要翻译： 一个示例性实施例是用相变材料填充通孔的方法。 所述方法步骤包括在衬底中形成底部电极，在所述底部电极上沉积介电层，以及在所述电介质层内形成通孔至所述底部电极的顶表面。 将基板加热至反应温度，并且在通孔内沉积第一相变材料前体。 第一前体被配置为在反应温度下在底部电极的顶表面上和在电介质层的顶表面上分解化学吸附物。 在第一前体之后，第二前体沉积在通孔内，在底部电极的顶表面上至少部分分解。
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公开(公告)号：US20120309159A1
公开(公告)日：2012-12-06
申请号：US13150559
申请日：2011-06-01
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L21/31144 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/1683
摘要： An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode.
摘要翻译： 一个示例性实施例是用相变材料填充通孔的方法。 所述方法步骤包括在衬底中形成底部电极，在所述底部电极上沉积介电层，以及在所述电介质层内形成通孔至所述底部电极的顶表面。 将基板加热至反应温度，并且在通孔内沉积第一相变材料前体。 第一前体被配置为在反应温度下在底部电极的顶表面上和在电介质层的顶表面上分解化学吸附物。 在第一前体之后，第二前体沉积在通孔内，在底部电极的顶表面上至少部分分解。
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3.发明申请Phase Change Materials for Applications that Require Fast Switching and High Endurance 审中-公开需要快速切换和高耐久性的应用的相变材料公开(公告)号：US20090230377A1
公开(公告)日：2009-09-17
申请号：US12357886
申请日：2009-01-22
IPC分类号： H01L47/00
CPC分类号： H01L45/148 , H01L45/06 , H01L45/1233 , H01L45/1625
摘要： A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution; wherein the memory device further includes a means for heating the phase change material.
摘要翻译： 使用相变材料作为存储介质的记忆装置，以固溶体为基础的锑作为溶剂的相变材料; 其中所述存储装置还包括用于加热所述相变材料的装置。
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4.发明授权Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 有权用于形成PCRAM和自对准回蚀工艺的自对准位线的方法公开(公告)号：US08273598B2
公开(公告)日：2012-09-25
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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5.发明授权Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process 失效用于形成PCRAM和自对准回蚀工艺的自对准位线的方法公开(公告)号：US08445313B2
公开(公告)日：2013-05-21
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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6.发明申请METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 有权用于形成用于PCRAM和自对准回退过程的自对准位线的方法公开(公告)号：US20120202333A1
公开(公告)日：2012-08-09
申请号：US13020051
申请日：2011-02-03
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/02
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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公开(公告)号：US20110108792A1
公开(公告)日：2011-05-12
申请号：US12616492
申请日：2009-11-11
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： A method for fabricating a phase change memory (PCM) cell includes forming a dielectric layer over an electrode, the electrode comprising an electrode material; forming a via hole in the dielectric layer such that the via hole extends down to the electrode; and growing a single crystal of a phase change material on the electrode in the via hole. A phase change memory (PCM) cell includes an electrode comprising an electrode material; a dielectric layer over the electrode; a via hole in the dielectric layer; and a single crystal of a phase change material located in the via hole, the single crystal contacting the electrode at the bottom of the via hole.
摘要翻译： 制造相变存储器（PCM）单元的方法包括在电极上形成电介质层，所述电极包括电极材料; 在电介质层中形成通孔，使得通孔向下延伸到电极; 以及在通孔中的电极上生长相变材料的单晶。 相变存储器（PCM）单元包括包括电极材料的电极; 电极上的电介质层; 介电层中的通孔; 以及位于通孔中的相变材料的单晶，单晶与通孔底部的电极接触。
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8.发明申请METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS 失效用于形成用于PCRAM和自对准回退过程的自对准位线的方法公开(公告)号：US20120276688A1
公开(公告)日：2012-11-01
申请号：US13546684
申请日：2012-07-11
申请人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
发明人： Matthew J. Breitwisch , Chieh-Fang Chen , Shih-Hung Chen , Eric A. Joseph , Chung Hon Lam , Michael F. Lofaro , Hsiang-Lan Lung , Alejandro G. Schrott , Min Yang
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.
摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。
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9.发明授权公开(公告)号：US08383501B2
公开(公告)日：2013-02-26
申请号：US13185055
申请日：2011-07-18
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译： 垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。 半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。 或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。 用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。
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公开(公告)号：US20130001500A1
公开(公告)日：2013-01-03
申请号：US13612552
申请日：2012-09-12
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
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