公开(公告)号：US20070104209A1

公开(公告)日：2007-05-10

申请号：US11594743

申请日：2006-11-09

Applicant: Chien-Hsien Wu ,  Yook-Khai Cheok ,  Eugene Opsasnick

Inventor： Chien-Hsien Wu ,  Yook-Khai Cheok ,  Eugene Opsasnick

IPC: H04L12/56 ,  H04J3/06

CPC classification number: G11C7/1039 ,  G06F12/0853 ,  G06F12/0855 ,  G06F13/1668 ,  G06F13/1689 ,  G11C7/1072 ,  H04L7/02 ,  H04L49/1546 ,  H04L49/3009

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.

Abstract translation: 用于处理数据的网络设备包括至少一个用于对输入数据执行切换功能的入口模块，用于将输入数据存储在存储器中的存储器管理单元和用于将输入数据发送到至少一个出口的至少一个出口模块。 存储器管理单元被配置为以网络设备的时钟速度接收数据，并且使用作为网络设备的时钟速度的倍数的倍增时钟速度将数据写入存储器，从存储器读出数据 倍增的时钟速度，并以网络设备的时钟速度向至少一个出口模块提供数据，其中使用相乘的时钟速度来采样网络设备的时钟速度以放置倍增时钟速度的域，并且 网络设备的时钟速度同步。

公开(公告)号：US08514875B2

公开(公告)日：2013-08-20

申请号：US11594743

申请日：2006-11-09

Applicant: Chien-Hsien Wu ,  Yook-Khai Cheok ,  Eugene Opsasnick

Inventor： Chien-Hsien Wu ,  Yook-Khai Cheok ,  Eugene Opsasnick

IPC: G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F13/16 ,  G06F12/08

CPC classification number: G11C7/1039 ,  G06F12/0853 ,  G06F12/0855 ,  G06F13/1668 ,  G06F13/1689 ,  G11C7/1072 ,  H04L7/02 ,  H04L49/1546 ,  H04L49/3009

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.

Abstract translation: 用于处理数据的网络设备包括至少一个用于对输入数据执行切换功能的入口模块，用于将输入数据存储在存储器中的存储器管理单元和用于将输入数据发送到至少一个出口的至少一个出口模块。 存储器管理单元被配置为以网络设备的时钟速度接收数据，并且使用作为网络设备的时钟速度的倍数的倍增时钟速度将数据写入存储器，从存储器读出数据 倍增的时钟速度，并以网络设备的时钟速度向至少一个出口模块提供数据，其中使用相乘的时钟速度来采样网络设备的时钟速度以放置倍增时钟速度的域，并且 网络设备的时钟速度同步。

公开(公告)号：US20090161693A1

公开(公告)日：2009-06-25

申请号：US11960982

申请日：2007-12-20

Applicant: Yook-Khai Cheok ,  Jillian (Yue) Yang ,  Yih-Chuan Chen ,  Michael Lau

Inventor： Yook-Khai Cheok ,  Jillian (Yue) Yang ,  Yih-Chuan Chen ,  Michael Lau

IPC: H04J3/16

CPC classification number: H04J3/1682 ,  H04L47/70 ,  H04L47/788 ,  H04L47/822

Abstract: The disclosed systems and methods relate to allocating bandwidth to a plurality of ports that access a shared resource. An exemplary system may comprise a multiplexer, a table, and a scheduling circuit. The table may define when a port has access to the shared resource. The table entries may be based on the number of ports with access to the shared resource and the required bandwidth in each of the ports. The scheduling circuit controls the multiplexer according to the table, and the ports may gain access to the shared resource one port at a time.

Abstract translation: 所公开的系统和方法涉及将带宽分配给访问共享资源的多个端口。 示例性系统可以包括多路复用器，表和调度电路。 该表可以定义端口何时可以访问共享资源。 表项可以基于访问共享资源的端口数量和每个端口中所需的带宽。 调度电路根据表控制多路复用器，并且端口可以一次访问共享资源一个端口。

公开(公告)号：US07111127B2

公开(公告)日：2006-09-19

申请号：US10744892

申请日：2003-12-23

Applicant: Kimming So ,  Chia-Cheng Choung ,  BaoBinh Truong ,  Yook-Khai Cheok

Inventor： Kimming So ,  Chia-Cheng Choung ,  BaoBinh Truong ,  Yook-Khai Cheok

IPC: G06F12/08

CPC classification number: G06F12/0855

Abstract: One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.

Abstract translation: 提出了一种或多种将连续数据存储性能提高到高速缓冲存储器中的方法和系统。 在一个实施例中，该方法包括在访问与至少第二存储指令相关联的标签阵列中的标签时将数据写入与至少第一存储指令相关联的数据阵列。 在一个实施例中，将连续数据存储处理到高速缓冲存储器中的方法包括更新高速缓冲存储器中的第一数据，同时在高速缓冲存储器中查找或识别第二数据。 在一个实施例中，用于改进CPU的数据存储指令的执行的系统包括使用最少数量条目的流水线缓冲器，用于更新与第一存储指令相关联的数据的数据阵列，以及用于查找的标签阵列 与第二存储指令相关联的数据。

公开(公告)号：US20060106946A1

公开(公告)日：2006-05-18

申请号：US11172799

申请日：2005-07-05

Applicant: Puneet Agarwal ,  Yook-Khai Cheok

Inventor： Puneet Agarwal ,  Yook-Khai Cheok

IPC: G06F15/16 ,  H04J3/24

CPC classification number: H04L69/16 ,  H04L69/161 ,  H04L69/166 ,  H04L2012/5652

Abstract: A hardware packets reassembly apparatus and method includes an ingress unit receiving and parsing a data packet, recognizing fragments corresponding to the data packet, and outputting control information of the fragments. An en-queue unit stores the control information of each fragment, links each related fragment based on the control information, and enqueues the data packet when all fragments are available corresponding to the data packet, wherein the data packet is enqueued only when all of the fragments corresponding to the data packet are available in a sequential order. A dequeue unit dequeues the data packet from a packet descriptor, and scheduling the data packet based on a corresponding class of service. An egress unit assembles all fragments corresponding to the data packet into a full packet and outputting the assembled data packet from an output port.

Abstract translation: 硬件分组重组装置和方法包括：入口单元，接收和解析数据分组，识别对应于数据分组的分段，并输出分片的控制信息。 队列单元存储每个片段的控制信息，基于控制信息链接每个相关片段，并且当与数据分组相对应的所有片段可用时，对数据分组进行排队，其中仅当所有片段 与数据包相对应的片段可以按顺序提供。 出队单元从数据包描述符中取出数据包，并根据相应的服务类别调度数据包。 出口单元将与数据分组相对应的所有片段组合成完整分组，并从输出端口输出组合的数据分组。

公开(公告)号：US20050015552A1

公开(公告)日：2005-01-20

申请号：US10744892

申请日：2003-12-23

Applicant: Kimming So ,  Chia-Cheng Choung ,  BaoBinh Truong ,  Yook-Khai Cheok

Inventor： Kimming So ,  Chia-Cheng Choung ,  BaoBinh Truong ,  Yook-Khai Cheok

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0855

Abstract: One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.

Abstract translation: 提出了一种或多种将连续数据存储性能提高到高速缓冲存储器中的方法和系统。 在一个实施例中，该方法包括在访问与至少第二存储指令相关联的标签阵列中的标签时将数据写入与至少第一存储指令相关联的数据阵列。 在一个实施例中，将连续数据存储处理到高速缓冲存储器中的方法包括更新高速缓冲存储器中的第一数据，同时在高速缓冲存储器中查找或识别第二数据。 在一个实施例中，用于改进CPU的数据存储指令的执行的系统包括使用最少数量条目的流水线缓冲器，用于更新与第一存储指令相关联的数据的数据阵列，以及用于查找的标签阵列 与第二存储指令相关联的数据。