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1.发明授权Processing of multiple cells in a network device with two reads and two writes on one clock cycle 有权在一个时钟周期内处理具有两次读取和两次写入的网络设备中的多个单元公开(公告)号：US08514875B2
公开(公告)日：2013-08-20
申请号：US11594743
申请日：2006-11-09
CPC分类号： G11C7/1039 , G06F12/0853 , G06F12/0855 , G06F13/1668 , G06F13/1689 , G11C7/1072 , H04L7/02 , H04L49/1546 , H04L49/3009
摘要： A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.
摘要翻译： 用于处理数据的网络设备包括至少一个用于对输入数据执行切换功能的入口模块，用于将输入数据存储在存储器中的存储器管理单元和用于将输入数据发送到至少一个出口的至少一个出口模块。 存储器管理单元被配置为以网络设备的时钟速度接收数据，并且使用作为网络设备的时钟速度的倍数的倍增时钟速度将数据写入存储器，从存储器读出数据 倍增的时钟速度，并以网络设备的时钟速度向至少一个出口模块提供数据，其中使用相乘的时钟速度来采样网络设备的时钟速度以放置倍增时钟速度的域，并且 网络设备的时钟速度同步。
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2.发明申请Processing of multiple cells in a network device with two reads and two writes on one clock cycle 有权在一个时钟周期内处理具有两次读取和两次写入的网络设备中的多个单元公开(公告)号：US20070104209A1
公开(公告)日：2007-05-10
申请号：US11594743
申请日：2006-11-09
CPC分类号： G11C7/1039 , G06F12/0853 , G06F12/0855 , G06F13/1668 , G06F13/1689 , G11C7/1072 , H04L7/02 , H04L49/1546 , H04L49/3009
摘要： A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.
摘要翻译： 用于处理数据的网络设备包括至少一个用于对输入数据执行切换功能的入口模块，用于将输入数据存储在存储器中的存储器管理单元和用于将输入数据发送到至少一个出口的至少一个出口模块。 存储器管理单元被配置为以网络设备的时钟速度接收数据，并且使用作为网络设备的时钟速度的倍数的倍增时钟速度将数据写入存储器，从存储器读出数据 倍增的时钟速度，并以网络设备的时钟速度向至少一个出口模块提供数据，其中使用相乘的时钟速度来采样网络设备的时钟速度以放置倍增时钟速度的域，并且 网络设备的时钟速度同步。
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3.发明授权Buffer management and flow control mechanism including packet-based dynamic thresholding 有权缓冲管理和流控制机制，包括基于分组的动态阈值公开(公告)号：US07953002B2
公开(公告)日：2011-05-31
申请号：US11595978
申请日：2006-11-13
申请人： Eugene Opsasnick
发明人： Eugene Opsasnick
IPC分类号： H04L12/26 , H04L1/00 , H04L12/28 , G06F15/173
CPC分类号： H04L47/10 , H04L47/2433 , H04L47/2441 , H04L47/266 , H04L47/30 , H04L47/32 , H04L49/205 , H04L49/3045 , H04L49/3072
摘要： A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one ingress module is configured to determine a priority for the incoming data, where that priority is mapped to a discrete number of priority groups and where the priority groups are determined on a per-port basis and provide guaranteed delivery or best throughput, and flow of data through the network device is controlled on a basis of at least one of the priority groups and assigned priorities.
摘要翻译： 用于处理数据的网络设备包括至少一个用于对输入数据执行切换功能的入口模块，用于存储输入数据的存储器管理单元和用于将输入数据发送到至少一个出口的至少一个出口模块。 所述至少一个入口模块被配置为确定所述输入数据的优先级，其中所述优先级被映射到离散数量的优先级组，并且优先级组在每个端口基础上确定并且提供有保证的传送或最佳吞吐量， 并且基于优先级组和分配的优先级中的至少一个来控制通过网络设备的数据流。
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公开(公告)号：US20060092845A1
公开(公告)日：2006-05-04
申请号：US11260232
申请日：2005-10-28
申请人： Bruce Kwan , Eugene Opsasnick , Puneet Agarwal
发明人： Bruce Kwan , Eugene Opsasnick , Puneet Agarwal
IPC分类号： H04J1/16
CPC分类号： H04L47/50
摘要： A service aware flow control apparatus and method for multiple classes of data packets. A flow control sender includes a buffer of an ingress port per Class Group or Class of Service (COS). A counter per COS tracks an amount of buffer utilization per ingress port per COS, and each counter comprises an XOFF threshold level of congestion and an XON threshold. A controller detects, during transmission of the data packets, a counter associated with a buffer for a particular COS has risen to be greater than or equal to the XOFF threshold level of congestion. A flow control receiver ceases transmission of the data packets to the buffer for the particular COS experiencing congestion and allowing transmission of the data packets corresponding to other COS in the flow control sender.
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5.发明申请公开(公告)号：US20140006822A1
公开(公告)日：2014-01-02
申请号：US13538144
申请日：2012-06-29
申请人： Wael DIAB , Nicholas Ilyadis , Eugene Opsasnick
发明人： Wael DIAB , Nicholas Ilyadis , Eugene Opsasnick
IPC分类号： G06F1/00
CPC分类号： H04L41/0816 , G06F1/3206 , G06F1/324 , H04L43/0882 , H04L43/0894 , Y02D10/126 , Y02D50/20
摘要： Embodiments are directed to saving power consumption in packet processing devices. A method for controlling power consumption of a packet processing device includes determining a power-save link utilization based upon one or more power-save enabled links of the packet processing device, determining an aggregate minimum processing bandwidth for the packet processing device based at least upon the determined power-save link utilization, and adjusting a processing capacity of the packet processing device based upon the determined aggregate minimum processing bandwidth, wherein the power consumption is changed by the adjusting. System and computer program product embodiments are also disclosed.
摘要翻译： 实施例涉及在分组处理设备中节省功耗。 一种用于控制分组处理设备的功耗的方法包括：基于分组处理设备的一个或多个节能使能链路确定节电链路利用率，至少基于所述分组处理设备确定所述分组处理设备的聚合最小处理带宽 确定的节电链路利用率，以及基于所确定的聚合最小处理带宽来调整分组处理设备的处理能力，其中通过调整改变功耗。 还公开了系统和计算机程序产品实施例。
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6.发明申请Buffer management and flow control mechanism including packet-based dynamic thresholding 有权缓冲管理和流控制机制，包括基于分组的动态阈值公开(公告)号：US20070104102A1
公开(公告)日：2007-05-10
申请号：US11595978
申请日：2006-11-13
申请人： Eugene Opsasnick
发明人： Eugene Opsasnick
CPC分类号： H04L47/10 , H04L47/2433 , H04L47/2441 , H04L47/266 , H04L47/30 , H04L47/32 , H04L49/205 , H04L49/3045 , H04L49/3072
摘要： A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one ingress module is configured to determine a priority for the incoming data, where that priority is mapped to a discrete number of priority groups and where the priority groups are determined on a per-port basis and provide guaranteed delivery or best throughput, and flow of data through the network device is controlled on a basis of at least one of the priority groups and assigned priorities.
摘要翻译： 用于处理数据的网络设备包括至少一个用于对输入数据执行切换功能的入口模块，用于存储输入数据的存储器管理单元和用于将输入数据发送到至少一个出口的至少一个出口模块。 所述至少一个入口模块被配置为确定所述输入数据的优先级，其中所述优先级被映射到离散数量的优先级组，并且优先级组在每个端口基础上确定并且提供有保证的传送或最佳吞吐量， 并且基于优先级组和分配的优先级中的至少一个来控制通过网络设备的数据流。
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7.发明申请公开(公告)号：US20140059303A1
公开(公告)日：2014-02-27
申请号：US13591919
申请日：2012-08-22
申请人： Michael LAU , Mark Griswold , Eugene Opsasnick
发明人： Michael LAU , Mark Griswold , Eugene Opsasnick
IPC分类号： G06F12/00
CPC分类号： H04L12/56 , G06F3/0689 , H04L49/00 , H04L49/90
摘要： Systems and methods of writing data to a buffer during a buffer cycle are described. The buffer has a plurality of buffer banks having various fill levels. The buffer determines a first portion of banks from the plurality of buffer banks. The first portion of banks unfilled banks. A rank can be assigned to each of the first portion of banks and a candidate set of banks chosen from the first portion of banks. A target bank is then chosen from the candidate set and the data is written to that bank. The ranking may be random. Furthermore, the target bank can be chosen based on ranking, fill level, or both.
摘要翻译： 描述了在缓冲器周期期间将数据写入缓冲器的系统和方法。 缓冲器具有多个具有各种填充量的缓冲器组。 缓冲器确定来自多个缓冲器组的存储体的第一部分。 银行的第一部分没有填满银行。 银行的第一部分中的每一个以及从银行的第一部分中选择的一组候选银行可以分配一个等级。 然后从候选集中选择目标银行，并将数据写入该银行。 排名可能是随机的。 此外，可以基于排名，填充水平或两者来选择目标银行。
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8.发明授权公开(公告)号：US09112727B2
公开(公告)日：2015-08-18
申请号：US13591919
申请日：2012-08-22
申请人： Michael Lau , Mark Griswold , Eugene Opsasnick
发明人： Michael Lau , Mark Griswold , Eugene Opsasnick
IPC分类号： G06F12/00 , H04L12/00 , H04L12/54 , H04L12/931 , G06F3/06
CPC分类号： H04L12/56 , G06F3/0689 , H04L49/00 , H04L49/90
摘要： Systems and methods of writing data to a buffer during a buffer cycle are described. The buffer has a plurality of buffer banks having various fill levels. The buffer determines a first portion of banks from the plurality of buffer banks. The first portion of banks unfilled banks. A rank can be assigned to each of the first portion of banks and a candidate set of banks chosen from the first portion of banks. A target bank is then chosen from the candidate set and the data is written to that bank. The ranking may be random. Furthermore, the target bank can be chosen based on ranking, fill level, or both.
摘要翻译： 描述了在缓冲器周期期间将数据写入缓冲器的系统和方法。 缓冲器具有多个具有各种填充量的缓冲器组。 缓冲器确定来自多个缓冲器组的存储体的第一部分。 银行的第一部分没有填满银行。 银行的第一部分中的每一个以及从银行的第一部分中选择的一组候选银行可以分配一个等级。 然后从候选集中选择目标银行，并将数据写入该银行。 排名可能是随机的。 此外，可以基于排名，填充水平或两者来选择目标银行。
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9.发明授权公开(公告)号：US09086878B2
公开(公告)日：2015-07-21
申请号：US13538144
申请日：2012-06-29
申请人： Wael Diab , Nicholas Ilyadis , Eugene Opsasnick
发明人： Wael Diab , Nicholas Ilyadis , Eugene Opsasnick
CPC分类号： H04L41/0816 , G06F1/3206 , G06F1/324 , H04L43/0882 , H04L43/0894 , Y02D10/126 , Y02D50/20
摘要： Embodiments are directed to saving power consumption in packet processing devices. A method for controlling power consumption of a packet processing device includes determining a power-save link utilization based upon one or more power-save enabled links of the packet processing device, determining an aggregate minimum processing bandwidth for the packet processing device based at least upon the determined power-save link utilization, and adjusting a processing capacity of the packet processing device based upon the determined aggregate minimum processing bandwidth, wherein the power consumption is changed by the adjusting. System and computer program product embodiments are also disclosed.
摘要翻译： 实施例涉及在分组处理设备中节省功耗。 一种用于控制分组处理设备的功耗的方法包括：基于分组处理设备的一个或多个节能使能链路确定节电链路利用率，至少基于所述分组处理设备确定所述分组处理设备的聚合最小处理带宽 确定的节电链路利用率，以及基于所确定的聚合最小处理带宽来调整分组处理设备的处理能力，其中通过调整改变功耗。 还公开了系统和计算机程序产品实施例。
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公开(公告)号：US08218546B2
公开(公告)日：2012-07-10
申请号：US11598116
申请日：2006-11-13
申请人： Eugene Opsasnick
发明人： Eugene Opsasnick
IPC分类号： H04L12/28
CPC分类号： H04L47/6215 , H04L45/7453 , H04L47/521 , H04L47/564 , H04L47/58 , H04L47/6225 , H04L47/623 , H04L47/6285 , H04L49/3027
摘要： A network device for processing packets includes at least one ingress module for performing switching functions on a packet, a memory management unit for storing the packet and at least one egress module for transmitting the packet to at least one port. The at least one egress module is configured to maintain multiple queues for the at least one port, including a purge queue, and to store the packet in the purge queue when an error condition is determined when the end of the packet is received by the at least one ingress module.
摘要翻译： 用于处理分组的网络设备包括至少一个用于在分组上执行切换功能的入口模块，用于存储分组的存储器管理单元和用于将分组发送到至少一个端口的至少一个出口模块。 所述至少一个出口模块被配置为为所述至少一个端口（包括清除队列）维护多个队列，并且当所述分组的结束被所述at 至少一个入口模块。
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